Search found 8 matches
- Mon Apr 26, 2021 5:19 pm
- Forum: CX16 General Chat
- Topic: Can the VERA's FPGA be reprogrammed?
- Replies: 35
- Views: 19082
Can the VERA's FPGA be reprogrammed?
<blockquote data-ipsquote="" class="ipsQuote" data-ipsquote-contentcommentid="8873" data-ipsquote-username="Wavicle" data-cite="Wavicle" data-ipsquote-userid="1585" data-ipsquote-timestamp="1616291267"><div> The dev team hasn't, to my knowledge, officially stated what the VERA's FPGA is, but the onl...
- Wed Aug 05, 2020 10:31 am
- Forum: Lounge
- Topic:
- Replies: -1
- Views:
Updating screen on vblank takes too long
<blockquote class="ipsQuote" data-ipsquote="" data-ipsquote-contentapp="forums" data-ipsquote-contentclass="forums_Topic" data-ipsquote-contentcommentid="1982" data-ipsquote-contentid="348" data-ipsquote-contenttype="forums" data-ipsquote-timestamp="1596560371" data-ipsquote-userid="17" data-ipsquot...
- Sun Jul 26, 2020 4:45 am
- Forum: CX16 General Chat
- Topic: Can the VERA's FPGA be reprogrammed?
- Replies: 35
- Views: 19082
Can the VERA's FPGA be reprogrammed?
On the real hardware, there will be a way to reprogram the FPGA image if necessary to fix any bugs that are discovered after release. (This involves putting a jumper on the VERA board to enable access to the flash chip from the CPU.) So yes, if you would like to hack around you can, it is (will be)...
- Sun Jul 26, 2020 4:40 am
- Forum: Lounge
- Topic:
- Replies: -1
- Views:
Some VERA questions
1. If the horizontal pixel counter equals DC_START the output will be enabled, at DC_STOP it will be disabled. So if DC_START is bigger than DC_STOP, DC_STOP is basically ignored and the image will be displayed up to the end of the line. 2. Sprites are rendered in order of their index, so higher in...
- Sun Jul 26, 2020 4:37 am
- Forum: Lounge
- Topic:
- Replies: -1
- Views:
320x240 resolution
I think in the end someone should create a test suite of programs to test the corner cases on both real hardware and the emulator to test they produce equal results. For the real hardware, in interlaced mode it only renders the lines that are actually displayed for that field. But regarding the lin...
- Sun Jul 26, 2020 4:33 am
- Forum: CX16 General Chat
- Topic: Hi from the Netherlands (X16 VERA Designer)
- Replies: 16
- Views: 7362
Hi from the Netherlands (X16 VERA Designer)
Eventually probably yes. But don't expect this until the system has been released and on the market for some while.
- Mon Jun 29, 2020 10:40 am
- Forum: Lounge
- Topic:
- Replies: -1
- Views:
Black area at bottom of emulator
The hardware really only has one output resolution: 640x480. 320x200 isn't a resolution that is natively supported by VERA. As far as I know the kernal has this 320x200 resolution as part of the GEOS drawing code, which Michael didn't yet update to make use of the full 240 lines height. As Stephon ...
- Wed May 20, 2020 4:58 am
- Forum: CX16 General Chat
- Topic: Hi from the Netherlands (X16 VERA Designer)
- Replies: 16
- Views: 7362
Hi from the Netherlands (X16 VERA Designer)
Hello all,
My name is Frank van den Hoef and I am responsible for the design of the VERA module (the audio, video and storage hardware module), which is part of the Commander X16.