Commander X16

But the solution you propose still doesn't deal with the CPU using the 8K bank at the time.  I'm just saying there's a real reason for a design change.

I don't think we've discussed whether the Vera can take a store (or fetch) per cycle, either... for that matter.

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I didn't explicitly say you had to use that FPGA and I realize that the current design precludes it.  But vera -> bank would allow direct loading of the bank from media... so it makes sense. The REU + GEOS (about the only thing other than TMP that used it) ... the thing that made it rock was that t...

So ... I've been watching with interest, but not contributing because I didn't see anything I needed to say.  I do now. I think the function of the 64/128 REU's memory transfer function is under-appreciated.  It's like a budget blitter chip.  Your memory design has 2M of memory in an 8k bottleneck....