Commander X16

There may be "false-positives" due to reflections - for instance the metal casing around the keyboard/mouse are also a large reflective surface. At certain angles, I noticed the FLIR was "seeing itself" (or some other object in the reflection - such as my own body, which ends up...

voidstar wrote: ↑Tue Jul 18, 2023 7:58 am It's an older C2 model - 5+yrs now. 320x240 is all it can muster.

Move the camera closer to the board.

This is really great work. Definitely shows the Yamaha could benefit from a heatsink to help extend its life.

Thanks Spargue! I’ve just sat down with a coffee and breakfast burrito at my local reservation breakfast shack to look at finalising this design when I saw your additional post here - much obliged. I hadn’t realised WE# needed to end a tad early so thanks for that. One thing I’m not sufficiently cl...

On my PC now and not on my phone. Noticed the WE doesn't use the PHI2 edge. WE# needs to end slightly early to grab the data or it all collapses in a fuzzy way and you get bad writes. OE doesn't need this latch as its grabbed from the CPU internally on PHY2 I'd recommend some inline resistors on the...

Just so I'm clear from having followed this interesting & spirited discussion... If I WRITE to the banked ROM space for banks above #0-#31 and I have an expansion card with RAM mapped in to the ROM space, the data that is written by the CPU will actually be stored in the RAM, assuming I've wire...

Just so I'm clear from having followed this interesting & spirited discussion... If I WRITE to the banked ROM space for banks above #0-#31 and I have an expansion card with RAM mapped in to the ROM space, the data that is written by the CPU will actually be stored in the RAM, assuming I've wire...

I'm the one that proposed using the VPB signal as an additional reset to the ROM bank latch and I looked at it fairly closely. Ultimately the decision was VPB as the only signal, which I disagree with but that's because I'd like an advanced debugger to insert itself after reset but before the CPU s...

Do expansion cards of any/all types, whether using the dedicated IO slots or accessing the full 64K address space seen by the CPU also get to 'see' the same banked ROM & RAM as the CPU does? I'm working on an expansion card design that could really do with accessing at least one of the 8K RAM b...

I might know where the confusion is coming from. 4 latch is now value before entering ISR (not bank 0), but ISR is still running assuming it's bank 0. The very beginning of the ISR, which is responsible for reading $0001, pushing it onto the stack, and setting $0001 to zero, is executing out of RAM...