What's the state of play with serial port support?

[BruceMcF]

38 minutes ago, TomXP411 said:

Can that hardware address devices in the expansion slots, or just the YM and SAA chips?

MaxLinear also has Motorola bus 8bit UARTS, but their 8bit UARTS other than the VLIO bus parts seem to be getting long in the tooth, so it you wanted a dual serial port 8bit bus UART from Maxlinear with 64+ FIFIO on both receive and transmit, you'd want to be flexible about accepting the Intel/Motorola bus versions.

MaxLinear's datasheets for their Intel/Motorola 8bit bus UARTS give the circuit. It seems like it would be possible from a single glue logic chip.

I don't have that circuit in front of me, but it seems like you could do it with a dual two bit pull down encoder, chip select and R/W to one encoder, two of the four outputs are /Read and /Write, chip select and ground to the other encoder, one of the outputs is /CS, so it's synchronous with  /Read /Write rather than leading it.

Similarly there's a quad logic gate that supports a similar circuit.

My idea was the absolute cheapest expansion card that gives you a second parallel/GPIO port and a serial port faster than just big banging a VIA. if you borrow the serial shift register already available on the User port, I think there's nothing going to beat a VIA and a MAX232 for drop ship price.

[LIV2]

There's also the SC28L92 DUART which is still produced by NXP & TI that several of us are using over on 6502.org. very simple to interface in "Motorola" mode

[BruceMcF]

6 hours ago, LIV2 said:

There's also the SC28L92 DUART which is still produced by NXP & TI that several of us are using over on 6502.org. very simple to interface in "Motorola" mode

I do like that I/M pin, that is more convenient than needing a circuit to generate /Read and /Write from R/W and /CE ... and I also see that you can use a Motorola R/W flag with the 8088 bus cycle.

I wonder whether the bus timings are OK for 8MHz operation at +5v, or whether use of the RDY line is needed to stretch the register access operations by a cycle (which would in effect be an actual Motorola bus interface).

[Lorin Millsap]

I do like that I/M pin, that is more convenient than needing a circuit to generate /Read and /Write from R/W and /CE ... and I also see that you can use a Motorola R/W flag with the 8088 bus cycle.
I wonder whether the bus timings are OK for 8MHz operation at +5v, or whether use of the RDY line is needed to stretch the register access operations by a cycle (which would in effect be an actual Motorola bus interface).

It will work just fine.


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[Michael Steil]

There is currently no support for RS232 in the X16 KERNAL.

• 
  Initially, the VIC-20/C64 software 6551 emulation was still in the source, but never working, because it needs tight integration with a timer on the 6522 and NMIs.
  


• 
  When VERA got an RS232 port integrated, the emulation was replaced with a VERA driver
  


• 
  When VERA removed the RS232 port again, that driver was removed from the KERNAL.
  

So we don't currently have any support for RS232 in the KERNAL.

That said, I'd love to have a software implementation, but it should be based on something like UP9600 rather than Commodore's VIC-20/C64 code. Pull request, anyone?

[TomXP411]

7 hours ago, Michael Steil said:

There is currently no support for RS232 in the X16 KERNAL.

• 
  Initially, the VIC-20/C64 software 6551 emulation was still in the source, but never working, because it needs tight integration with a timer on the 6522 and NMIs.
  


• 
  When VERA got an RS232 port integrated, the emulation was replaced with a VERA driver
  


• 
  When VERA removed the RS232 port again, that driver was removed from the KERNAL.
  

So we don't currently have any support for RS232 in the KERNAL.



That said, I'd love to have a software implementation, but it should be based on something like UP9600 rather than Commodore's VIC-20/C64 code. Pull request, anyone?

UP9600 relies on a hardware shifter in the CIAs. Is there a free bit shifter in any of the Commander's VIAs to make that happen? That would certainly be preferable to software serial. 

The other obvious question is... do we have a pinout of the User port? It would be difficult to implement anything without knowing the pins to use. 

Otherwise, the end result is that we need either a port of the VIC code, or we need to modify code from one of the open source terminal programs. 

And if we're going to do software serial on the User port, maybe it's worth the effort to include SIO as well. In fact, SIO is actually cheaper to implement, since it doesn't require complicated timing. You just strobe the clock line and read the data lines. I'd almost rather do that than RS232, then use an external Arduino to provide the hardware UART interface. Or, if that's not acceptable, maybe provide 1, 2, and 4 bit SIO as options, using the OPEN string to change the protocol. 



For example:

OPEN 2,2,2,"9600,N,8,1" opens an RS-232 port at 9600 baud. 

OPEN 2,2,2,"SIO,4" opens a 4-bit SIO port. 

Both would communicate through device number 2, but the driver would modulate the pins differently, depending on the access mode specified in the filename string. 

 

 

[Lorin Millsap]

Most of the pins on the second VIA are free and are mapped to the user port. This includes the shift registers.

The first VIA is mostly occupied for critical system functions.


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[BruceMcF]

On 7/13/2020 at 3:27 AM, Michael Steil said:

There is currently no support for RS232 in the X16 KERNAL.

• 
  Initially, the VIC-20/C64 software 6551 emulation was still in the source, but never working, because it needs tight integration with a timer on the 6522 and NMIs.
  


• 
  When VERA got an RS232 port integrated, the emulation was replaced with a VERA driver
  


• 
  When VERA removed the RS232 port again, that driver was removed from the KERNAL.
  

So we don't currently have any support for RS232 in the KERNAL.



That said, I'd love to have a software implementation, but it should be based on something like UP9600 rather than Commodore's VIC-20/C64 code. Pull request, anyone?

UP9600 required two serial shift registers. That was [edit: one reason] why it was incompatible with the C128 "burst" IEC mode.

It is the 2400bps routines which do not require the serial shift registers. That seems like it would give with very little doubt 9600bps and hopefully{+} 19.2Kbps without requiring the shift registers. If someone wants to look into that, there is an advertised "reliable" C64 2400bps routine at GitHub: https://github.com/nanoflite/c64-up2400-cc65  

{+ Since there were few modems operating at speeds between 2400baud and 9600baud, and I don't have the original Transactor article documenting the technique, it's not entirely clear how fast those routines could have been pushed in the C64 ... they might have sufficient headroom that 19.2kbps is comfortably within the capabilities of an 8MHz VIA even if there are vagaries of interrupt responsiveness.}

 

[Andre]

On 7/7/2020 at 5:10 AM, TomXP411 said:

People bring up the 6551 because this is the chip used by the Swiftlink and compatible serial cartridges for the Commodore 64. This design is simple, only needs a few components, and the code is already out there to support this chip. Someone could port a terminal program from the C64 to the Commander very quickly by just modifying the screen output code and the I/O address for the serial port. 



At first, I was against using the WDC 6551, due to the register bug, but as long as is this is only on the transmit register, it's not actually a problem: programs just need to wait for 10 baud units of time before writing another byte to the data register. There are several ways this can be done, including using a programmable timer on one of the VIA chips.



I have written code for the 16550 UART as well, although it's been 20+ years. However, there aren't any public, baseline designs we can draw from when building interface cards, like there are with the 16550. The 16550 is not designed for the 6502 bus, and so it will require additional hardware to couple to this CPU. 



 



 



 

http://www.6502.org/users/andre/icaphw/c64ser.html

Baseline, public design to integrate a UART into a 6502 system.

[Andre]

On 7/13/2020 at 6:05 AM, BruceMcF said:

UP9600 required two serial shift registers. That was why it was incompatible with the C128 "burst" IEC mode.

Not only that. It is also using the NMI, that is, in general, incompatible with precise IEC bus timing.