C256 Foenix "Gen X"

[BruceMcF]

Reaction when reading that: "More frequent updates? What are you smok... Oh! Discord! So THAT is where all the action is."

Anyone NOT connecting to the C256 project on Discord is going to have the opposite reaction. On YouTube and on the web site, updates are not just infrequent, but also hard to find.

And if there are any systems actually for sale, that is also left as a puzzle mystery on the site. The only system on the first page is the GenX, which is "coming", and only if you are persistent and check out page 2 do you find pre-orders for a U board, " being redesigned" due to some vague FPGA parts issue.

Also, while working hardware may have shipped, no actually working systems have shipped if you have to load software by injecting with a USB debug function. Until/unless you can load and run software from the SD card, it's not really a working system (I say "until/unless" because for all I know you can, it's just that the information on the issue has not yet been updated).



(Edit) One side effect of having seperate main system software authors and hardware designers is that the process of developing the emulator to allow software development to proceed while hardware issues are being sorted doesn't take time away from those same hardware issues being sorted out. So while it is up in the air whether there will be an actually usable system running on the Feonix U in October (assuming it does ship in October), I have no doubt that the CX16 will have a usable system running when it ships.

[paulscottrobson]

On 6/13/2021 at 11:15 PM, EMwhite said:

• 
  I'm not familiar with the CPU but it looks like a superset of the 6502
  

 

16 bit superset. It still as the same basic registers, but A and XY can be 8 or 16 bit in operation, it can mimic a 65c02 perfectly or run in 16 bit mode (where I think it's best, except for 8 bit string and other data handling, which there isn't a huge amount of). There are some extra addressing modes suitable for C and obviously 24 bit versions of them. There are also a few tricks which allow you to move zero page about and the like. If you can program the 6502 the 65816 is no real stretch.

[paulscottrobson]

12 hours ago, m00dawg said:

Sometimes I get a little frustrated with the X16 team over lack of updates because they have SUCH A GIFT with the exposure the X16 has whereas Stephanie has had to do it the hard way and she's a brilliant engineer but is perhaps in need of a marketer (which kinda sucks I have a distaste for marketing but if people don't know about your product....). I do feel, and I know it's a sensitive subject on the team, but the very sparse updates on the X16 - well I'll put it this way it tends to crush my momentum with my Command Tracker when I haven't heard much in a while. Doesn't need to be a lot, just a minor update.

I always thought it a shame that Stefany and David didn't join forces. Stefany's an awesome engineer ; she's done a huge amount all by herself on the hardware. David is more software, is great at the 'team building' sort of stuff, has a much bigger audience. It's hard going being a one woman hardware machine - and of course there's always the possibility (god forbid) that Stefany could have a mishap or other external events which would probably kill the project. Even if the hardware is open sourced much of it is in her head I suspect.

I recall from "Dream Computer #1" that they talked about it and some retro meet somewhere, but they were too far apart, this being David's mark one design - the cheap $50 design with minimal hardware.

CX16 has moved much closer to Stefany's sort of design in many ways, as more and more has gone on the FPGA, there's the 6502 RAM/ROM and one of the sound chips (?) and a VIA and most else is in the FPGA. Which isn't far from the Foenix design (though I think it may have DMA, not sure without checking).

Too late now, I suspect, to combine forces.

I can see why she's produced a redesign but it's in danger of fragmenting the fairly small community.

[BruceMcF]

13 hours ago, paulscottrobson said:

I always thought it a shame that Stefany and David didn't join forces. Stefany's an awesome engineer ; she's done a huge amount all by herself on the hardware. David is more software, is great at the 'team building' sort of stuff, has a much bigger audience. It's hard going being a one woman hardware machine - and of course there's always the possibility (god forbid) that Stefany could have a mishap or other external events which would probably kill the project. Even if the hardware is open sourced much of it is in her head I suspect.



I recall from "Dream Computer #1" that they talked about it and some retro meet somewhere, but they were too far apart, this being David's mark one design - the cheap $50 design with minimal hardware.



CX16 has moved much closer to Stefany's sort of design in many ways, as more and more has gone on the FPGA, there's the 6502 RAM/ROM and one of the sound chips (?) and a VIA and most else is in the FPGA. Which isn't far from the Foenix design (though I think it may have DMA, not sure without checking).



Too late now, I suspect, to combine forces.



I can see why she's produced a redesign but it's in danger of fragmenting the fairly small community.

It has a bucketload of DMA, since there is a DMA handler for system memory and a DMA handler for video memory ... Video RAM is, AFAICT, static RAM and the way she gets the bandwidth she needs to layout up 32 sprites and four text/tile layers and two bitmap layers on a 14MHz bus is to access 32bits at once with four 1Mx8bit SRAM chips accessed in parallel by the Video FPGA, Vickey.

As a side note, when you are tallying the "non-FPGA" parts of the CX16 system design, you are skipping all of the addressing logic in the CX16p being done with glue logic, and all the system resources handled by the other VIA (assuming your count of a VIA is the mostly free VIA available on the User Port). Also the 8bit, through pin PS microcontroller they added.

I reckon the design that was abandoned before the current 64K memory map was settled on was a lot closer to Stefany's sort of design, it apparently had three or four FPGA's or CPLD's of various sorts. It would have had one FPGA or CPLD grabbing the high byte from the data bus of the 65816, which would have been doing some of the work of Gavin on the Feonix.

However, one similar feature was having the PCM / CODEC at up to 48KHz frequency on FPGA (though in the separate sound FPGA in the Feonix), though of course the Feonix has the System RAM DMA to feed it, and they both also have a "SID like" sound generator ... the Feonix being much closer with an FPGA stereo SID simulator except without the analog filters, in the CX16 with it's "it's kind of SID like if you squint" 16 channel PSG with NEITHER ADSR nor filters.

[However, even with combining FPGA chips in the U (and I would suppose, the GenX), the Video generator and Sound master/generator "custom chips" in the Feonix are still different chips ... so the Video RAM DMA and system RAM DMA are still in different FPGA ... rather than the Video and Sound generator combined into a single "custom chip" in the CX16.]

Stefany's "U" design is also moving toward the CX16 Vera in having an FPGA SD card interface, AFAICT to allow the "U" design to make the Super I/O chip an optional extra.

I would have personally preferred the AY3's and have the Vera chip handle the feeding of data to the AY3's if they couldn't work out glue logic to do it, ditching the PSG, which AFAIU would have been closer to Stefany's original Beatrice FPGA, but alas, and alack, it was not to be.

(Edit) Before I forget, the sound FPGA Beatrice can trigger the sound chips it controls simultaneously, which is a lot stronger assurance of no perceptible lag than "well, there IS a lag but hopefully it's not perceptible.' If you see reference to Gabe, that is the single FPGA that merge the functions of the system master FPGA Gavin and the music master FPGA (mistress?) Beatrice.





 

[paulscottrobson]

Thanks. I (obviously !) didn't know that, I'd just had a casual look at it.

Better than I thought.

[rje]

Stefany's design would be of little use to me -- I'm not the target demographic.  Of all those neat features, only the 16 bit processor would appeal to me.

I feel the same way toward the MEGA 65 ("I'm not the target demographic"), although I find it fascinating and really enjoyed reading the development blog.

It is interesting that, perhaps inevitably, the Foenix and the X16 would drift slightly closer to each other.

 

 

[codewar65]

Not for me either. Too many moving parts.

You only need one versatile sound option. One versatile video option. One versatile game controller option. etc.

Bolting on kitchen sinks will confuse and fragment developers, force users to buy controllers and cards for every scenario.

[Cyber]

15 hours ago, BruceMcF said:

I would have personally preferred the AY3's and have the Vera chip handle the feeding of data to the AY3's if they couldn't work out glue logic to do it

I was also sad to hear AY go. AY can't work on frequencies higher than 2 MHz, and David clearly said they don't want any additional logic between bus and sound chip. No point to discuss this, I just wanted to sympathize and join little club of AY. ) 

[BruceMcF]

6 hours ago, Cyber said:

I was also sad to hear AY go. AY can't work on frequencies higher than 2 MHz, and David clearly said they don't want any additional logic between bus and sound chip. No point to discuss this, I just wanted to sympathize and join little club of AY. ) 

Yeah, just lamenting. If the FPGA drives the timing and selection, you only need one demux between the data and address lines to the AY3 data/address bus, since the one not being selected will ignore the data anyway. So there might not have been enough pins to do it like the Beatrice chip and have the FPGA bus master the sound chips (pins is likely why the sound chip and video chip are in still in different FPGA's), but you could still hold the CPU with RDY and just demux the address and data bus values being asserted in sequence with the AY3.

But it's water under the bridge. If people really want some AY3's, they need to slap some in an expansion board and add the circuit to stretch and demux the CPU data and address lines themselves. And without the motherboard design limitations, that can just be in a single CPLD, so it can just have memory mapped registers and buffer the data in the CPLD until the AY3 is ready to receive it.

[rje]

2 hours ago, BruceMcF said:

If people really want some AY3's, they need to slap some in an expansion board and add the circuit to stretch and demux the CPU data and address lines themselves. [...]

The expansion slots are, I think, a good way to democratize and defer part of the design process.  If people want X badly enough, then Y.

Limits the compromising down to "what's the base framework".  Although I do note that 8BG paid attention to his own episodes, and noted that apps tend to develop off of the base platform for maximum market-- so include the things you WANT, when you design the base model.