Bus Pinout on Proto #3

[Scott Robison]

34 minutes ago, TomXP411 said:

It’s probably the opposite. The 816’s stack and Direct Page can be moved. So it may be that they need to be initialized as part of the startup procedure. . 

In emulation mode it is supposed to start with ZP & stack at their well defined 6502 locations. I've never used an '816, just based on my reading. The opcode issue could be real if any of the bit set / clear extensions are used in the kernal or BASIC as emulation mode apparently doesn't support them, though they are available in native mode.

[BruceMcF]

27 minutes ago, Scott Robison said:

In emulation mode it is supposed to start with ZP & stack at their well defined 6502 locations. I've never used an '816, just based on my reading. The opcode issue could be real if any of the bit set / clear extensions are used in the kernal or BASIC as emulation mode apparently doesn't support them, though they are available in native mode.

 

1 hour ago, TomXP411 said:

It’s probably the opposite. The 816’s stack and Direct Page can be moved. So it may be that they need to be initialized as part of the startup procedure. . 

Yeah, I've only every used an 816 in an emulator. Bit Set / Clear extensions are one possibility ... they obviously would not have been in the original codebase, so it's whether they have been added ... another, given the issues with timings and the fact that Vera might be quicker to read than other chips on the board, is the $00 on the data bus during the first phase tangling something up.

Another might be a "tacit bug" ...  a misdirected branch "executing" an unimplemented opcode as a NOP, but it is a 65816 opcode, which if NOT in the 65c02 opcodes actually performs it's native mode action, 65c02 even if in emulation mode. IOW, emulation mode is emulating 65C02 OPCODE functions, not "emulating a 65C02".

[TomXP411]

2 hours ago, Scott Robison said:

In emulation mode it is supposed to start with ZP & stack at their well defined 6502 locations. I've never used an '816, just based on my reading. The opcode issue could be real if any of the bit set / clear extensions are used in the kernal or BASIC as emulation mode apparently doesn't support them, though they are available in native mode.

That would do it, I suspect.

Personally, I'm just very disappointed that they didn't go with the 816 from the start. It only takes one extra chip to make it work as intended, and we wouldn't have the silly 4K banks. Instead, we'd have up to 16MB of RAM in 64K banks.

I started designing a (very non-Commodore like) OS for the 816 back when Stefany got started with the Feonix. Building an OS to operate with multiple 64K banks and 16-bit reads and writes is much, much easier and faster than the way the CX16 was designed. I get why Michael and David went with something familiar, but the 65816 with a 24 bit address space would have been so much better, the difference is almost night and day. 

[BruceMcF]

Note that the bit set/clear instructions that are not available in the 65816 are unavailable in any mode ... they are the Rockwell extensions, and those opcodes do other things in the 65C816 instruction set.

[Scott Robison]

3 hours ago, BruceMcF said:

Note that the bit set/clear instructions that are not available in the 65816 are unavailable in any mode ... they are the Rockwell extensions, and those opcodes do other things in the 65C816 instruction set.

Thanks for the clarification. That makes a lot more sense. I was under the impression from quick reading that was not the case.

[BruceMcF]

These are the $x7 and $xF opcodes, RMB0-RMB7, SMB0-SMB7, BBR0-BBR7 and BBS0-BBS7. In the 65816, these are four new address modes for the 8 main accumulator operations, ORA, AND, EOR, ADC, STA, LDA, CMP, SBC ... op [d]; op [d],Y; op al; and op al,X ... 24bit indirect and post-indexed addressing, 24bit absolute and X-indexed absolute addressing.

 

[Scott Robison]

1 hour ago, BruceMcF said:

These are the $x7 and $xF opcodes, RMB0-RMB7, SMB0-SMB7, BBR0-BBR7 and BBS0-BBS7. In the 65816, these are four new address modes for the 8 main accumulator operations, ORA, AND, EOR, ADC, STA, LDA, CMP, SBC ... op [d]; op [d],Y; op al; and op al,X ... 24bit indirect and post-indexed addressing, 24bit absolute and X-indexed absolute addressing.

I was subconsciously aware of this, but having never used an '816 didn't think it through thoroughly. It is confusing in part due to the fact (as I understand it) that 65c02 didn't include the bit instructions, but later added them and introduced the 65sc02 that didn't have them. So rather than leaving 65c02 alone, it was updated and a new part was created to keep the older functionality, and that part no longer exists.

Again, as I understand it. I may be way off base, it's hard to find the complete information because at this point, all details of 65c02 document it as including the bit instructions but originally it was a proper subset of 65c816.

[BruceMcF]

3 hours ago, Scott Robison said:

I was subconsciously aware of this, but having never used an '816 didn't think it through thoroughly. It is confusing in part due to the fact (as I understand it) that 65c02 didn't include the bit instructions, but later added them and introduced the 65sc02 that didn't have them. So rather than leaving 65c02 alone, it was updated and a new part was created to keep the older functionality, and that part no longer exists.



Again, as I understand it. I may be way off base, it's hard to find the complete information because at this point, all details of 65c02 document it as including the bit instructions but originally it was a proper subset of 65c816.

Yes, Rockwell added these instructions to the original 65C02. WDC added a few other instructions. Rockwell had a big order for their version of the chip (IIRC it was a French telecoms company, but that may be wrong) ... and so WDC added the individual bit instructions to their version of the 65C02 so they could be second source for that company.

However, that was just to gain that market. The 65C02 instructions that the 65816 "emulation mode" emulates is their original WDC65C02 design. Those are specialized instructions primarily for using the 6502 in a controller application with I/O memory mapped into part of the zero page, and with the relocatable direct page, that wasn't in line with what the 65816 was targeting.

I forget whether Western originated the TSB and TRB instructions or whether they included those following an earlier 65C02 design, but those are much more flexible instructions in addressing and occupy much less of the instruction set, even if they usually have to be preceded by an immediate load instruction.

[Scott Robison]

5 minutes ago, BruceMcF said:

Yes, Rockwell added these instructions to the original 65C02. WDC added a few other instructions. Rockwell had a big order for their version of the chip (IIRC it was a French telecoms company, but that may be wrong) ... and so WDC added the individual bit instructions to their version of the 65C02 so they could be second source for that company.

I wonder why WDC didn't create a 65c02e (for enhanced, or x for extended, or r for Rockwell...) and make that the updated part. Adding them to the existing product seems more confusing that it needs to be.

[BruceMcF]

9 minutes ago, Scott Robison said:

I wonder why WDC didn't create a 65c02e (for enhanced, or x for extended, or r for Rockwell...) and make that the updated part. Adding them to the existing product seems more confusing that it needs to be.

It didn't modify the operation of their existing design except for the $x7 and $xF opcodes no longer being NOPs, and Rockwell sold theirs as 65C02's (maybe R65C02?), so it likely made sense in selling the updated chips as a second source to the target company. They weren't selling the two versions side by side, after all ... the 6502's at that time were selling briskly enough for industrial control boards that a month of overlapping inventories for a fully backwards compatible upgrade wasn't a problem.

Also IIRC (so no guarantees), the 65CS02 was not about the change in instruction set, it was about revising the chip to be fully static ... though at the same time additional instructions were added. The Rockwell and Western Design versions were fully static from the outset, so they had no need to single out their fully static version.

One thing I certainly don't recall is whether MOS or Fairchild or somebody else took the lead in the CMOS version of the CPU.