6502 RISC instruction set running at 3.4ghz..
6502 RISC instruction set running at 3.4ghz..
An example of that is how the subtract function is simply use the add circuit, but inverting the bits of the byte being subtracted. But without inverting the carry flag.
"But that is not the two's complement negative, to get the two's complement negative you need to add one!"
Oh, yeah, so for subtract, you set carry for borrow clear. If there is a borrow, leave carry clear for borrow set.
"But that makes no sense, that makes the borrow flag the inverse of the carry flag!"
Yes, exactly. And saves the transistors needed to invert the carry flag.
"But the CMP instruction needs to subtract too?"
Yes, and it needs to subtract with borrow clear. It doesn't care whether that sets the carry input to one or to zero.
6502 RISC instruction set running at 3.4ghz..
10 minutes ago, BruceMcF said:
An example of that is how the subtract function is simply invert the bits of the byte being subtracted.
"But that is not the two's complement negative, to get the two's complement negative you need to add one!"
Oh, yeah, so for subtract, you set carry for borrow clear. If there is a borrow, leave carry clear for borrow set.
"But that makes no sense, that makes the borrow flag the inverse of the carry flag!"
Yes, exactly. And saves a lot of transistors.
... and requires you to do a CLC or SEC every time you do simple math, unless you know the state of the carry flag already.
This is exactly the kind of tradeoff you get when you simply a system to save money... but obviously the result was worth it.
6502 RISC instruction set running at 3.4ghz..
Quite, using ADC for both ADC and ADD, SBC for both SBC and SUB means there are two operations that simply don't have to be provided, which is even more transistors saved.
Similarly, arithmetic shift right is less commonly needed, and if it is can be done by a routine, so leave it out.
6502 RISC instruction set running at 3.4ghz..
I can't imagine a descendant of the 6502 produced for the desktop today remaining with 8-bit registers and data bus, 16-bit address bus, and no extra ports and busses working out for a general audience outside of library terminals or something like the IT arrangement of the Continental Hotel, especially if this beast has a superscalar, multicore architecture. Way too many computing architectural compromises would be required to make it work.
On the other hand, if either Commodore or Western Design Center had ca. the late 70s committed to something like Andre Fachat's 65K project...
6502 RISC instruction set running at 3.4ghz..
On 7/24/2021 at 12:24 AM, Kalvan said:
I can't imagine a descendant of the 6502 produced for the desktop today remaining with 8-bit registers and data bus, 16-bit address bus, and no extra ports and busses working out for a general audience outside of library terminals or something like the IT arrangement of the Continental Hotel, especially if this beast has a superscalar, multicore architecture. Way too many computing architectural compromises would be required to make it work.
On the other hand, if either Commodore or Western Design Center had ca. the late 70s committed to something like Andre Fachat's 65K project...
Now, I should stress that I was not engaged in a serious design proposal up there, but rather playing a less than totally serious what if game that "just coincidentally" ended up with something like a CX16 memory map.
But, yeah, it's text manipulation or some other 8bit oriented date in any event -- it's not oriented to video -- given that the notion of single word Unicode has pretty much universally given way to UTF8 ... and it would have to be something that is leveraging the fact that there are VERY FEW TRANSISTORS in the 6502 hardware design ... so it's got to be a whole hell of a lot of 6502 cores on a chip ... so in that respect more like an array of GPU cores in some GPU designs, but targeting a text processing rather than video processing dedicate application.
So it really is a 6502 core with 512bytes of on-chip cache as dedicated zero page and stack page, taking advantage of the very small hardware footprint of the 6502 to be able to give it much more persistent local storage than is typically feasible with a processor array chip design ... and then the L2 cache is shared out between the cores somehow ... say, locations $0000-$0007 are byte L2 segment registers for the 64K address space in 8K segments, giving up to 2MB L2 cache. $0008/$0009 controls whether they are R/W, Read Only or Write Only, so that an individual bank can be used as a pipeline between two cores.
Actual RAM is accessed using a DMA controller accessed in the zero page address space of "one in N" of the 6502 cores, which controls the reading and writing between the L2 core and RAM.
All quite implausible, but fun to think about.