Remapping zeropage/stack?

[Andre]

Sorry I'm late to the game, I am wondering why the zeropage and/or stack cannot be remapped to a different memory location (except I have overseen something) like e.g. in the C128.

I would make things like transient programs, or even multitasking so much easier, especially as the X16 is supposed to be 8 times faster than the old CBMs.

Thanks

[Lorin Millsap]

Sorry I'm late to the game, I am wondering why the zeropage and/or stack cannot be remapped to a different memory location (except I have overseen something) like e.g. in the C128.
I would make things like transient programs, or even multitasking so much easier, especially as the X16 is supposed to be 8 times faster than the old CBMs.
Thanks

Neither can be relocated under the current model.


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[Andre]

22 minutes ago, Lorin Millsap said:

Neither can be relocated under the current model.

 

That's what I noticed. So has this been discussed as an option? If so, what was the rationale to exclude this feature?

[Lorin Millsap]

That's what I noticed. So has this been discussed as an option? If so, what was the rationale to exclude this feature?

Because it wasn’t excluded. It would have to be implemented. Those are cpu functions and the X16 doesn’t have a MMU.


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[Andre]

5 minutes ago, Lorin Millsap said:

Because it wasn’t excluded. It would have to be implemented. Those are cpu functions and the X16 doesn’t have a MMU.

 

The X16 remaps an 8k window of RAM and a 16k window of ROM in the upper area. Remapping e.g. the lowest part could work similarly even without an MMU.

But I understand, someone has to implement it.

[Lorin Millsap]

The X16 remaps an 8k window of RAM and a 16k window of ROM in the upper area. Remapping e.g. the lowest part could work similarly even without an MMU.
But I understand, someone has to implement it.

Well short answer is it doesn’t have it. Technically remapping and banking are not the same thing. And remember the X16 is supposed to be simple.


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[Guybrush]

Implementing it is a problem because address decoding and banking (the stuff that's handled by the PLA in C64) is currently done by discrete logic on the motherboard (a handful of off-the-shelf electronic components). Remapping the stack and/or zeropage would require even more logic and a major overhaul of the motherboard layout. Eventually it would be easier to use the same sort of hacks that are used for PLA replacements: EPROM or another FPGA. Not sure it's realistic at this point in the development of the machine.

[TomXP411]

This would have been easy to do with a 65816, and it would have even made multitasking possible. But the 6502 simply does not have the hardware to remap Zero Page, and one of the design goals for the CX16 was to KISS. 

The banking logic in the 8K upper memory space is done by manipulating the address pins of the 512K (or 2MB) RAM modules with one of the VIA chips. The lower 13 bits come straight off the CPU's address bus, and the upper 8 bits are selected using the VIA parallel port. 

To do the same thing with Zero Page would require more chip select logic, additional memory chips, and another VIA manage the bank selection... or a custom MMU, like Commodore built for the C128. Since either option would be more expensive, I can see why they left that out. 

 

 

[Lorin Millsap]

This would have been easy to do with a 65816, and it would have even made multitasking possible. But the 6502 simply does not have the hardware to remap Zero Page, and one of the design goals for the CX16 was to KISS. 
The banking logic in the 8K upper memory space is done by manipulating the address pins of the 512K (or 2MB) RAM modules with one of the VIA chips. The lower 13 bits come straight off the CPU's address bus, and the upper 8 bits are selected using the VIA parallel port. 
To do the same thing with Zero Page would require more chip select logic, additional memory chips, and another VIA manage the bank selection... or a custom MMU, like Commodore built for the C128. Since either option would be more expensive, I can see why they left that out. 
 
 

Actually that’s no longer true. The banking is done without using the VIAs at all. It is now selected using latches shadowed at $00 and $01. This freed up the valuable VIA pins.


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[BruceMcF]

On 7/16/2020 at 6:51 AM, Andre said:

The X16 remaps an 8k window of RAM and a 16k window of ROM in the upper area. Remapping e.g. the lowest part could work similarly even without an MMU.



But I understand, someone has to implement it.

It actually doesn't REmap anything. Those windows are hardwired. An address in $C000-$FFFF triggers the chip select for ROM, the lower 14 bits are bused to the CPU address bus, the upper 5 bits are connected straight to the ROM segment latch. An address in $A000-$BFFF triggers what seems likely to be a 2-4 active low fanout from the upper two bits of the RAM segment latch, the lower six bits of the RAM segment latch are connected directly to the appropriate address lines of the SRAM, the bottom 13 bits are bused to the CPU address bus.

Each additional window is more glue logic and more chips and a bigger BOM.SUPPOSE you had a 2-4 fanout that is selected by A15=1, than combining the top two selects gives you the ROM select, the second select is directly the High RAM fan-out select (so both of those select ladders are only two deep), and the first select line can select the detect for the I/O page when A8-A13=1.

Now an entire additional detection has been set up for writing to $0000 and $0001, in the other half of the address space (those can be blind latches, because the RAM still stores the data).



Not only would detecting page zero and page 1 reads AND writes add direct additional complexity, you'd need somewhere to put it. AND you'd need redirect the physical address to one of the areas of RAM covered over (the I/O page, the High RAM or the ROM window). AND you'd need to protect that part of Low RAM from being overwritten when accessing that Window.



That extra physical design just so people don't have to learn how to use BASE,X and BASE,Y and (BASE),Y stacks probably doesn't seem worth the extra trouble.

If the unused three bits in the ROM register latch were used for anything, rather than remapping the zero and one page, I'd prefer if they turned off the $9F00-$9FFF, $A000-$BFFF and $C000-$DFFF selects and allowed the Low RAM "underneath" to be active for reads as well as writes ($E000-$FFFF ought to be left alone, since the interrupt vectors are at the top of the ROM space, plus there are only three bits to spare).