Memory Map

Johan Kårlin · Post by **Johan Kårlin** » Sat Jul 18, 2020 6:23 pm

I am sure there are good reasons for all decisions concerning the memory map. But to be curious, I am wondering about two things:

1. Zeropage $00 and $01 will be used for memory bank settings and $03-$7f will be available for the user. Why not locate the memory bank settings to $7e and $7f and leave $00-$7d to the user? It seems like a cleaner layout to me.

2. The I/O area is located to $9f00-$9fff, then banked ram starts at $a000. Why not locate the I/O area to $0400 giving the user approcimately extra 8K of continous memory (if bank 0 is used)?

Lorin Millsap · Post by **Lorin Millsap** » Sat Jul 18, 2020 7:53 pm

I am sure there are good reasons for all decisions concerning the memory map. But to be curious, I am wondering about two things:
1. Zeropage $00 and $01 will be used for memory bank settings and $03-$7f will be available for the user. Why not locate the memory bank settings to $7e and $7f and leave $00-$7d to the user? It seems like a cleaner layout to me.
2. The I/O area is located to $9f00-$9fff, then banked ram starts at $a000. Why not locate the I/O area to $0400 giving the user approcimately extra 8K of continous memory (if bank 0 is used)?

1. To do so would make the logic more complex. This ends up being the same two ZP locations the C64 uses anyway.
2. We looked at mapping IO elsewhere but found that doing so adds a lot more complexity which slows everything down and uses more parts. Having more contiguous memory doesn’t make sense if it’s not actually contiguous.

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Johan Kårlin · Post by **Johan Kårlin** » Sun Jul 19, 2020 6:56 am

Ok, I get the point. No big deal anyway. I am glad I didn’t hard code the location of my zero page variables though : ). I’ll just move them two bytes upwards in memory. Thanks for all your good work!

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Andre · Post by **Andre** » Sun Jul 19, 2020 8:34 am

1 hour ago, Johan Kårlin said:

Ok, I get the point. No big deal anyway. I am glad I didn’t hard code the location of my zero page variables though : ). I’ll just move them two bytes upwards in memory. Thanks for all your good work!

Hardcode zeropage locations? I hope you're using some modern tools like relocatable binaries?

Johan Kårlin · Post by **Johan Kårlin** » Sun Jul 19, 2020 8:52 am

What I mean is that there are no instructions like LDA $00 in my assembly source code. Instead I use constants like ZP0 = $0, ZP1 = $1 etc. I’ll just redefine them to ZP0 = $2, ZP1 = $3...

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BruceMcF · Post by **BruceMcF** » Sun Jul 19, 2020 1:02 pm

18 hours ago, Johan Kårlin said:

I am sure there are good reasons for all decisions concerning the memory map. But to be curious, I am wondering about two things:

1. Zeropage $00 and $01 will be used for memory bank settings and $03-$7f will be available for the user. Why not locate the memory bank settings to $7e and $7f and leave $00-$7d to the user? It seems like a cleaner layout to me.

2. The I/O area is located to $9f00-$9fff, then banked ram starts at $a000. Why not locate the I/O area to $0400 giving the user approcimately extra 8K of continous memory (if bank 0 is used)?

$00/$01 is the cleaner layout. A program that doesn't use the KERNAL would have $02-$FF contiguous with the current design, two discontinuous blocks of $00-$7D, $80-$FF with yours. The two cleanest locations are $00/$01 and $FE/$FF, and the second interferes data structures that lap over into the bottom of the stack page (where in some applications the full stack page is not required for the hardware stack).

It's also one of the simpler pair of bytes to generate a /CS for, just feed R/W and A1-A15 through a pair of 8bit line drivers and wire-or them.

You are right about $0300 or $0400 being a better place for the I/O page, but with the ROM at A13-A15=%11x, and the High RAM at A13-A15=%101, having the I/O at A13-A15=%100 seems likely to be easier to detect sufficiently fast. For example, the 00 line from an active low 2-4 decoder could be wire-ored with the output of three 2->1 Nand gates on A8/A9, A10/A11, and A12/A12 to select the I/O address fanout without a delay from multistage logiic (that is, if quad Nand gates happen to come in suitably fast logic ... what with CPLDs and FPGAs, fast glue logic doesn't always have all of the classical 74xx options).

Johan Kårlin · Post by **Johan Kårlin** » Sun Jul 19, 2020 2:57 pm

I see your point about the zeropage, I didn’t think about the case when the program wasn’t using KERNAL. Thanks also for your explanation about the hardware reasons for the location of the I/O area even if I am not able to fully understand it.