Commander X8 Disussion

[Calculon]

On 12/29/2021 at 2:27 PM, martinot said:

Is the VERA and X8 code open source and available for usage?

They are not open source.

[BruceMcF]

On 12/29/2021 at 1:28 AM, Wavicle said:

.. sourcing the FPGA and STM32 microcontroller (necessary unless you have another way to program the SPI flash) are not so easy these days.

Adafruit has "Programming SPI flash with an FT232H breakout", which is interesting on the point in parentheses.

[Wavicle]

On 12/29/2021 at 2:27 PM, martinot said:

Is the VERA and X8 code open source and available for usage?

The X8 repos were public about a year ago; it's unclear to me what the licenses were at the time. I cloned the hardware repos which seemed to contain all of VERA except for the 6502 bus interface. Frank has since either removed the repos or made them non-public.

[Wavicle]

On 12/30/2021 at 9:18 AM, BruceMcF said:

Adafruit has "Programming SPI flash with an FT232H breakout", which is interesting on the point in parentheses.

Depending on what your time/money/hobbyist-enjoyment ratios are, one might consider grabbing a TL866-II+ programmer with SOIC adapters. I picked one up off of Amazon a few years ago for $80. There is a Chinese OEM clone manufacturer of these so they're being sold under a dozen (probably two dozen) different brand names, but they're all identical hardware. It has reasonable software support, optional open source tools, and can program many different devices.

[lydon]

Will the HDL of the Commander X8 be available for porting to other FPGA platforms?

[Wavicle]

On 2/9/2022 at 6:52 AM, lydon said:

Will the HDL of the Commander X8 be available for porting to other FPGA platforms?

The HDL was briefly public on Frank's GitHub and there are a couple of forks of it still available. Only gotcha I saw in there that would affect FPGA porting is that unless you choose an FPGA with a large SRAM (the iCE40UP5K has two 16x32Kbit single ported, synchronous SRAM blocks) you'll need to tack on an external 32-bit SRAM with an access time ~20ns or better. There are plenty of affordable SRAM components that fulfill this requirement, you will also need at least 52 pins dedicated to the external memory. Keeping all other things fixed, that's a lower bound of 90 external IO pins.

[Lasagna]

On 2/9/2022 at 8:01 PM, Wavicle said:

The HDL was briefly public on Frank's GitHub and there are a couple of forks of it still available. Only gotcha I saw in there that would affect FPGA porting is that unless you choose an FPGA with a large SRAM (the iCE40UP5K has two 16x32Kbit single ported, synchronous SRAM blocks) you'll need to tack on an external 32-bit SRAM with an access time ~20ns or better. There are plenty of affordable SRAM components that fulfill this requirement, you will also need at least 52 pins dedicated to the external memory. Keeping all other things fixed, that's a lower bound of 90 external IO pins.

The Full VERA HDL is available now.

[Scott Robison]

On 3/14/2022 at 9:14 AM, Lasagna said:

The Full VERA HDL is available now.

And just to make sure people understand: the VERA HDL as intended for the X16 is available, which is not the same as the X8 that was being discussed previously.

At present it is available for study but without an open license that would allow it's use in other distributed projects.

[SlithyMatt]

On 3/14/2022 at 11:52 AM, Scott Robison said:

At present it is available for study but without an open license that would allow it's use in other distributed projects

Update: it now has an MIT license, which is very liberal: https://github.com/fvdhoef/vera-module/blob/rev4/LICENSE

[Scott Robison]

On 3/14/2022 at 11:19 AM, SlithyMatt said:

Update: it now has an MIT license, which is very liberal: https://github.com/fvdhoef/vera-module/blob/rev4/LICENSE

Things change so quickly.