improved IEC?
improved IEC?
Tecnically speaking when CX16 listens to the bus, which timing can be accepted by the standard protocol?
As a pure and odd theory could the standard protocol be made into a 2bit bus? in which the clock line works as usual but two bits are sent in the data and srq lines?
improved IEC?
On 10/26/2022 at 12:59 PM, Fabio said:
Tecnically speaking when CX16 listens to the bus, which timing can be accepted by the standard protocol?
As a pure and odd theory could the standard protocol be made into a 2bit bus? in which the clock line works as usual but two bits are sent in the data and srq lines?
The burst loader protocol is faster, since it is a protocol where recipient acknowledges receipt and then the sender can send another bit, rather than running at a clock rate set to accommodate the slowest device that may be on the serial link.
So if you have an SD2IEC type device built on an ATTiny with a 12MHz clock and replace it with one with a 20MHz clock, the top speed of that device in burst mode goes up. If you have a bit banged IEC run by a 65C02 running at 8MHz and upgrade to a VIA#1 hardware-assisted big banged IEC, the top speed of the X16 side of the burst mode goes up.
Also, since it's an already standard protocol, burst mode would have a larger ecosystem. A burst mode SD2IEC kind of device also works on a C128, or on a C64 with the User Port supported burst mode, and an X16 with burst mode also allows a real 1571 to be accessed faster than a 1541. It makes a 1581-clone a combined device for both retro C128 and X16 owners, and pooling multiple niches together might be what gets it over the economies of scale hurdle.
improved IEC?
On 10/26/2022 at 7:03 PM, BruceMcF said:
The burst loader protocol is faster, since it is a protocol where recipient acknowledges receipt and then the sender can send another bit, rather than running at a clock rate set to accommodate the slowest device that may be on the serial link.
wow !
where can be found further documentation on the burst protocol?
improved IEC?
On 10/26/2022 at 1:24 PM, Fabio said:
wow !
where can be found further documentation on the burst protocol?
The burst mode is covered Pasi Ojala in presenting his burst fastloader for the C64 (with User Port support).
Note that the same modification wouldn't be able to be done for the stock X16, since the C64 has a CIA, so there is no CNT pin in VIA#1. But the equivalent can be done with CB1 and CB2, with CB1 taking the role of CNT and CB2 taking the role of SP.
So the routine would have to be modified for the VIA hardware registers as opposed to the CIA registers, but the same basic approach can be followed, if CB1 and CB2 are available from a X16 motherboard User Port pin header.
improved IEC?
On 10/26/2022 at 2:01 PM, BruceMcF said:
The burst mode is covered Pasi Ojala in presenting his burst fastloader for the C64 (with User Port support).
Note that the same modification wouldn't be able to be done for the stock X16, since the C64 has a CIA, so there is no CNT pin in VIA#1. But the equivalent can be done with CB1 and CB2, with CB1 taking the role of CNT and CB2 taking the role of SP.
So the routine would have to be modified for the VIA hardware registers as opposed to the CIA registers, but the same basic approach can be followed, if CB1 and CB2 are available from a X16 motherboard User Port pin header.
If the updated I/O section of the PRG is correct, bit banging burst mode is supported via the CB1 line connected to SRQ, but the fastest burst mode is not supported. @Kevin Williams evidently does not have the CB2 line connected to IECDATA. In regular mode it would be set to input (so that it floats), in burstloader mode it would be set to input for input mode, in output mode the regular DATA is set to input (so IT floats) and the serial shift register is output in burst mode.