Future proofing for faster 6502 ie 14 or 100 MHz
Future proofing for faster 6502 ie 14 or 100 MHz
A video from the 8-bit guy video mentioned a problem with the sound chips not being able to handle bus speeds faster than 1-2 MHz. The approach taken to handle this seems to be system clock division. But another approach would be to put a latch register that is activated only upon write access to make the data values persist longer than the faster CPU bus cycle. Reading is done by two accesses, the first one to make the slower section get the read signal and then a few cycles later another read cycle to read the actual data. Ie LDA $1234 NOP NOP NOP NOP LDA $1234 ..
Alternatives are bus hold or interrupt driven read operation.
https://hackaday.com/2021/10/15/heres-a-100-mhz-pin-compatible-6502-replacement/
The idea would be to make it possible to swap the CPU for a significantly faster one without any major hardware modifications.
Future proofing for faster 6502 ie 14 or 100 MHz
The solution to address the problem was addition of a clock stretching circuit. It could be done with a parallel bus latching circuit, but I think you're understating the design complexity. You need at least two latches, one for the data bus and one for the address and control signals, a bus transceiver to prevent the logic on the slow side from driving the data bus, and the logic to detect/decode accesses to those. Potentially 4 ICs plus a complex software interface scheme... or we could stick with clock stretching circuit which uses a single IC and is transparent to software.
Future proofing for faster 6502 ie 14 or 100 MHz
Yes there is 14mhz wdc and 100mhz (fpga or arm emulation). I think best will be to have 8mhz first than in next models better cpus for next years.
For example:
Commander X16 - 8mhz wdc, 2mb ram, Vera+fm
2022-2023
Commander X16-II - 14mhz wdc, 4mb ram, Vera2+fm
2023-2024
Commande X16-EGS - 65816 - 20mhz wdc, 16mb ram, SuperVera+fm+DreamBlaster/Wavetable
2024-2025
Commander X16 Portable - fpga 6502 / 80mhz, 32mb ram, SuperVera with build in fm (system on chip - 1 chip version)
Commander X16 Mini - fpga 6502 / 80mhz, 32mb ram, SuperVera with build in fm (system on chip - 1 chip version)
2025-2026
Also low cost / DIY KIT:
Commander X16 Lite - 4mhz wdc, 256kb ram, Vera
Future proofing for faster 6502 ie 14 or 100 MHz
On 11/5/2022 at 12:03 AM, Matej said:
I think best will be to have 8mhz first than in next models better cpus for next years.
I don't think the X16 will develop the same way as the X86, 68000 or ARM CPUs changed/progressed computers and other devices. I believe that the Gen 1/2/3 boards will more or less be at the same computing power and meet the design and desire goals set out for it. There is such a small market for retro PCs compared to the general market, so I don't see the development demand for a faster "old" computer.
That being said, it doesn't stop anyone from developing the X16 further. One can dream ?
Future proofing for faster 6502 ie 14 or 100 MHz
(reconsidered this post, so, mostly deleted)
Bottom line: I dunno what "future proofing" 30 year old (ish) tech even means.
Future proofing for faster 6502 ie 14 or 100 MHz
@x16tial Future proofing as in making future improvements or changes possible.
Ask any PC owner about the limit of DMA on the ISA bus to the first 16 MB necessitating the use of bounce buffers. The same happened with DMA with PCI bus which is limited to the first 4 GB of memory. The storage capacity was limited to 32 MB originally, and after that all kinds of weird limits until they broke the 128 GB limit. i80386 motherboards needed clock doubler diode to make 80486 plugin CPU possible.
In essence it's a kind of architectural planning to avoid dead ends. It can sometimes be seen in datasheets as "reserved bits" or signals, enabling the manufacturer to assign them new capabilities later.
Any CPU booster likely will have to utilize on board (D)RAM because the bus likely will be limited. And then there's the question of handling of chips that can't do anything faster than 1-2 MHz bus clock. Software may also need a standardized mechanism to tell how fast the CPU runs. Also perhaps someone wants to add bus expanders etc.
Future proofing for faster 6502 ie 14 or 100 MHz
It's fairly obvious what the general term means, but when you consider my whole sentence, the "30 year old (ish) tech" part, well, we're IN the future of this tech, by about 30 years.
Re: Future proofing for faster 6502 ie 14 or 100 MHz
The next step on this "future proofing" is sorting out the jumpers you need to cap the speed when you are using the through-pin SRAM that they are using, which cannot be accessed at a 14MHz 6502 bus cycle, and of course while the VIA is rated for 14MHz as well, it surely wouldn't work at 100MHz.
But it's not just that they are in the process of building the first set of 100 "release candidate" Phase 1 boards, so it's far too late to make any of these changes to Phase 1. It's also that a stable development platform (like the Vic-20 or Commodore 64 represented) is part of what they are aiming for.
The way to support "a faster 65C02 clock" is to design a similar system around a faster system clock. We know that while rated at 14MHz, with the process that they are using now, new 65C02 and VIAs seem to be able to handle 16MHz comfortable. However, the widely available new through pin 512K SRAM cannot run at 16MHz, so you get a SMB SRAM.
And the "slow bus" peripherals supported by latching could use a single CPLD that also integrates the glue logic functions. You might have more complex logic that carves out Slow RAM from a single 1MB SRAM.
And you play with other things to better suits a different set of "how modern can this retro system be and still be retro" answers that you personally answer.
And in the end, it's just not binary compatible with the X16.
I expect the Commander X16 will have a lot more visibility and a lot bigger hobbyist developer ecosystem.
But if you've integrated a Vera FPGA into the board, and then set things up so that it is relatively easy to port "many" X16 programs, that means your hobbyist project is not limited to just the programs you can write yourself.
But it's not just that they are in the process of building the first set of 100 "release candidate" Phase 1 boards, so it's far too late to make any of these changes to Phase 1. It's also that a stable development platform (like the Vic-20 or Commodore 64 represented) is part of what they are aiming for.
The way to support "a faster 65C02 clock" is to design a similar system around a faster system clock. We know that while rated at 14MHz, with the process that they are using now, new 65C02 and VIAs seem to be able to handle 16MHz comfortable. However, the widely available new through pin 512K SRAM cannot run at 16MHz, so you get a SMB SRAM.
And the "slow bus" peripherals supported by latching could use a single CPLD that also integrates the glue logic functions. You might have more complex logic that carves out Slow RAM from a single 1MB SRAM.
And you play with other things to better suits a different set of "how modern can this retro system be and still be retro" answers that you personally answer.
And in the end, it's just not binary compatible with the X16.
I expect the Commander X16 will have a lot more visibility and a lot bigger hobbyist developer ecosystem.
But if you've integrated a Vera FPGA into the board, and then set things up so that it is relatively easy to port "many" X16 programs, that means your hobbyist project is not limited to just the programs you can write yourself.
Re: Future proofing for faster 6502 ie 14 or 100 MHz
As Bruce mentions, it's the "discreet through hole chips" design that stops you from going fast, and It's ALL the chips, really... ROM, RAM, the majority of the 6502 peripheral chips... so at best, you're faced with redesigning the core of the board onto an FPGA of some stripe just for the select logic...
The approach of the 100MHz 6502 module is to replace the 6502 itself with an FPGA that then pulls the ROM and RAM into itself on reset. As long as you're going there, you might as well just use the FPGA as the entirety of the core design.
Of course, that design stopped being an X16 at the very start of that process.
The question then becomes "What makes it retro?" For many, it's the discreet chip through hole design itself and the Commodore PET / VIC20 / C64 functionality. And that's fine! That's the "Commander X16" and it fills that niche quite well.
What makes it retro for me is the use of the 6502 and making the core system as bone simple as possible program wise. What makes that usable as a "system" is the VERA module and the SD card interface. Does the 6502 need to be in it's own "discreet chip" or even "through hole?" No. "6502" as I see it, is an ISA (Instruction Set Architecture) which could just as easily be in it's own chip design or implemented as a block in an FPGA.
Ultimately, it's like one of those choice triangles where you are presented with 3 choices, then told you have to pick 2. You can't have it all, you have to choose what's important based on your own interpretation of "important."
The approach of the 100MHz 6502 module is to replace the 6502 itself with an FPGA that then pulls the ROM and RAM into itself on reset. As long as you're going there, you might as well just use the FPGA as the entirety of the core design.
Of course, that design stopped being an X16 at the very start of that process.
The question then becomes "What makes it retro?" For many, it's the discreet chip through hole design itself and the Commodore PET / VIC20 / C64 functionality. And that's fine! That's the "Commander X16" and it fills that niche quite well.
What makes it retro for me is the use of the 6502 and making the core system as bone simple as possible program wise. What makes that usable as a "system" is the VERA module and the SD card interface. Does the 6502 need to be in it's own "discreet chip" or even "through hole?" No. "6502" as I see it, is an ISA (Instruction Set Architecture) which could just as easily be in it's own chip design or implemented as a block in an FPGA.
Ultimately, it's like one of those choice triangles where you are presented with 3 choices, then told you have to pick 2. You can't have it all, you have to choose what's important based on your own interpretation of "important."
Re: Future proofing for faster 6502 ie 14 or 100 MHz
Through hole RAM is the killer for going as fast as the ASIC 65C02 would allow, because there are very few cycles when a 65C02 is not interacting with RAM. If you had a shadow-ROM set-up with 10ns SRAM (which would be SMB), then ROM wouldn't be an issue and 10ns means you have not only all of the first phase of the clock cycle but much of the second phase so long as its the RAM chip select that settles low last.Daedalus wrote: ↑Sun Jan 22, 2023 6:09 pm As Bruce mentions, it's the "discreet through hole chips" design that stops you from going fast, and It's ALL the chips, really... ROM, RAM, the majority of the 6502 peripheral chips... so at best, you're faced with redesigning the core of the board onto an FPGA of some stripe just for the select logic...
Yes the three "Phases" of the project support people who settle on different answers to that question, with Phase 2 dropping the through hole requirement possibly easing the ASIC requirement for glue logic replaced by a CPLD, and Phase 3 dropping the ASIC CPU/VIA/etc. requirement. But since each later phase would be designed to target direct compatibility with Phase 1, the Phase 1 design constraints are binding for the Commander X16 project itself....What makes it retro for me is the use of the 6502 and making the core system as bone simple as possible program wise. What makes that usable as a "system" is the VERA module and the SD card interface. Does the 6502 need to be in it's own "discreet chip" or even "through hole?" No. "6502" as I see it, is an ISA (Instruction Set Architecture) which could just as easily be in it's own chip design or implemented as a block in an FPGA.