Clock division register

[Bound]

Hi there ,

one suggestion from myself . Why not to add clock divider and control division from dedicated register ?. This modification will let us to use slower devices such as SID chip . 

cheers

[StinkerB06]

Why not put a clock divider on the expansion card (if that's how you're supplying the SID chip)?

[BruceMcF]

It's a 65c02, so the RDY flag works for both reads and writes. An expansion card can pull RDY low when it is selected and have a counter on the system clock to release the RDY for however many cycles it needs before releasing it. This is lower overhead, because it doesn't require CPU intervention, and means ONLY the bus cycles accessing the slow device registers are affected. Slowing down the system clock slows down memory reads/writes and instruction execution.

To be sure, as explained by Lorin in an earlier thread, DMA access of the system bus is more complex than this, but latching PHI2&SEL=0 to RDY until a divider countdown is done is straightforward. They thought this through when they redesigned the C02 mask, that since it's fully static, freezing it at the start of PHI2=0 fixes the "read only" problem with the NMOS 6502 RDY line.

 

[BruceMcF]

2 minutes ago, BruceMcF said:

 

[Bound]

I had that done in my 65c816 sbc long time ago, and that worked quite good . When CPU reboot clock was set to 1MHZ that allowed system to boot from the slow eeprom and copy it to the RAM , then clock divider was dynamically controlled by writing data to divider register.

for example to run SID’s song play routine I slow down the cpu clock to 1MHZ , then run play subroutine and roll back divider register to original state. So if you had source of interrupts in my case 50hz you could run SID songs from C64 without any changes .

cheers

[BruceMcF]

1 hour ago, Bound said:

I had that done in my 65c816 sbc long time ago, and that worked quite good . When CPU reboot clock was set to 1MHZ that allowed system to boot from the slow eeprom and copy it to the RAM , then clock divider was dynamically controlled by writing data to divider register.



for example to run SID’s song play routine I slow down the cpu clock to 1MHZ , then run play subroutine and roll back divider register to original state. So if you had source of interrupts in my case 50hz you could run SID songs from C64 without any changes .



cheers

Not saying it won't work, just that it's not the efficient way to do it for a chip on an expansion card that needs slower register access. Booting up with slow EEPROM or FlashROM is a different issue ... they avoid the problem by not outrunning the FlashROM