Interested in developing a simple DMA controller

[BruceRMcF]

I had worked out a timing diagram for RAM some time ago. The RAM access is very tight needing every bit of that 30ns. The ROM timing is slightly less tight having about 5ns of breathing room - this is because ROM chip select decode is a single NAND gate. In either case, they have their respective data ready by the required 10ns setup time before the PHI2 negative edge.


X16_RAM_Timing.png

Props for that. So there is no wiggle room on the RAM decode.

So it might be that a 6x clock is a design approach to explore, since the first internal cycle would satisfy address hold times from the end of the previous clock and assert the address than the 65C02 itself would do.

I guess there would in any event by a start-up cycle required, to master the bus with BE, so both the Read and the Write pipeline might start in the "previous" cycle, allowing the address to be asserted in (say) the second or third cycle of a state machine, but at the start of the second internal clock in the Phi2=0 phase.