Need more info for JT51 a ym2151 compatible FPGA implementation.

[GTR3QQ]

The core is listed on github. But there is nothing regarding actually building one your self. Like the one 8bitguy shows in the April,2023 video, google search came out blank. No one is selling or listed it.
All I can find is one user in this forum says he is able to build one him self and his daughter can help him with smt soldering.

viewtopic.php?p=26565&hilit=ym2151#top


How he managed to get one? Is it the same as the one 8bit guy shown?

Do I have to brew my own implementation using Spartan 3 compatible chips?

[JimmyDansbo]

Wavicle is the guy who designed the YM2151 compatible FPGA implementation, that's why he has it

It seems he still have some issues with it, if you join the discord, you can follow along on his journey. He updates often with his troubles and findings.
Here is your invitation to the discord server.

[Wavicle]

The core is listed on github. But there is nothing regarding actually building one your self. Like the one 8bitguy shows in the April,2023 video, google search came out blank. No one is selling or listed it.
All I can find is one user in this forum says he is able to build one him self and his daughter can help him with smt soldering.

viewtopic.php?p=26565&hilit=ym2151#top


How he managed to get one? Is it the same as the one 8bit guy shown?

Do I have to brew my own implementation using Spartan 3 compatible chips?

It is indeed the same as the one 8bit guy showed. I know because I built that one and mailed it to him just in the nick of time to make it into the video.

I suppose you could make your own using Spartan 3 FPGAs. I used a Lattice iCE40UP5K.

[Daedalus]

Wavicle, you used the same Ice40up5k that's in the VERA for that? Now I'm interested.

I've been working on implementing the 65c02 ISA onto an "Icestick" dev board (The FPGA is a Lattice Ice40hx1k, basically a baby sibling of the Ice40up5k.) My implementation isn't impressive at all, I'm sure I'm making every error in the book as I've never used FPGAs or verilog before... but my crap code is enough to start the soft CPU, execute the reset vector and run 65c02 opcodes with all the registers and addressing modes. It works well enough and is fast enough that I'm confident that FPGAs are the future.

My eventual goal at this stage is to implement a twin FPGA system where where one runs the CPU and it's support, and the other focuses on the video and sound. The Icestick was an obvious choice due to it's relation to the existing VERA FPGA and it's ease of use, I've just been using APIO and the open source command line tools it manages for development.

So, my question is: How much of the Ice40up5k's resources did it take to implement the YM2151?

[GTR3QQ]

Wavicle, you used the same Ice40up5k that's in the VERA for that? Now I'm interested.

I've been working on implementing the 65c02 ISA onto an "Icestick" dev board (The FPGA is a Lattice Ice40hx1k, basically a baby sibling of the Ice40up5k.) My implementation isn't impressive at all, I'm sure I'm making every error in the book as I've never used FPGAs or verilog before... but my crap code is enough to start the soft CPU, execute the reset vector and run 65c02 opcodes with all the registers and addressing modes. It works well enough and is fast enough that I'm confident that FPGAs are the future.

My eventual goal at this stage is to implement a twin FPGA system where where one runs the CPU and it's support, and the other focuses on the video and sound. The Icestick was an obvious choice due to it's relation to the existing VERA FPGA and it's ease of use, I've just been using APIO and the open source command line tools it manages for development.

So, my question is: How much of the Ice40up5k's resources did it take to implement the YM2151?

I think you need to mention @Wavicle.
don't know if this is useful, but the github repo have Spartan 3 usage listed.
https://github.com/jotego/jt51/blob/mas ... an%203.txt

[GTR3QQ]

Wavicle is the guy who designed the YM2151 compatible FPGA implementation, that's why he has it

It seems he still have some issues with it, if you join the discord, you can follow along on his journey. He updates often with his troubles and findings.
Here is your invitation to the discord server.

Thanks.

[GTR3QQ]

The core is listed on github. But there is nothing regarding actually building one your self. Like the one 8bitguy shows in the April,2023 video, google search came out blank. No one is selling or listed it.
All I can find is one user in this forum says he is able to build one him self and his daughter can help him with smt soldering.

viewtopic.php?p=26565&hilit=ym2151#top


How he managed to get one? Is it the same as the one 8bit guy shown?

Do I have to brew my own implementation using Spartan 3 compatible chips?

It is indeed the same as the one 8bit guy showed. I know because I built that one and mailed it to him just in the nick of time to make it into the video.

I suppose you could make your own using Spartan 3 FPGAs. I used a Lattice iCE40UP5K.

I just learn that apparently Ym2151 can break subtly? Like your number 10 chip.
So it is pivotal to roll the FPGA replacement.
But how? unlike sid, ym2151 is fully digitized. How do you get a busted LFO while everything else is working? I'm more familiar with chip build with CMOS like ym3812, they either works perfectly or don't work at all.
Is like yamaha added too much phosphate or boron like CBM did with SID chips? Or NMOS just more prone to failure, like more susceptible to unstable voltage source.
Could it just a fluke? dirty socket/pins? single bit flip event?