Expansion slots

[spargue]

It should, since the cartridge ROMs are reliant on that behavior.

It should retain the state or should go high impedance?

[TomXP411]

As I said, cartridges work, so you can infer that the on-board ROM goes high impedance when the ROM bank is out of range for the on-board ROM.

Valid bank numbers for the on-board ROM are 0-31, so bank 32+ should leave the on-board rom de-selected, or in a high-z state.

[spargue]

As I said, cartridges work, so you can infer that the on-board ROM goes high impedance when the ROM bank is out of range for the on-board ROM.

Valid bank numbers for the on-board ROM are 0-31, so bank 32+ should leave the on-board rom de-selected, or in a high-z state.

I'm not asking if the cartridge goes into high impedence when the address is out of range; this would be expected behaviour as all rom/ram does this.
I'm asking if when an expansion cartridge sets BE low, does the rom bank pins also go high impedence from the latch so an expansion card can access rom banks independently or does it always drive the bus?

[TomXP411]

You already stated the answer in your question. I'm not sure what else you want me to say, here...

The [ROM] goes into high impedance when the address is out of range; this would be expected behavior as all rom/ram does this

[spargue]

You already stated the answer in your question. I'm not sure what else you want me to say, here...

The [ROM] goes into high impedance when the address is out of range; this would be expected behavior as all rom/ram does this

I'm not sure if there's a language barrier here or if you're just being maliciously incompetent.

When the BE pin is pulled low from the expansion slot the CPU places the address, data, and R/W pins into a high-Z state. My question is does the latch that stores the ROMB address also go into a high-Z state or does it still present the bank address?

please read all of the question.

[picosecond]

My question is does the latch that stores the ROMB address also go into a high-Z state or does it still present the bank address?

BE's only connections are the expansion slots and the 65C02. BE does not affect the ROM bank address latch. It always presents the bank address.

I also found your question unclear before this last clarification. You owe Tom an apology.

[BruceRMcF]

... I'm asking if when an expansion cartridge sets BE low, does the rom bank pins also go high impedence from the latch so an expansion card can access rom banks independently or does it always drive the bus?

The premise of the question, "so an expansion card can access ROM banks independently" is wrong.

A bus mastering card would not access ROM banks independently by replacing the ROM bank latch, it would access ROM banks independently by writing to the ROM latch at $0001. Ditto independent access to the HighRAM.

[TomXP411]

... I'm asking if when an expansion cartridge sets BE low, does the rom bank pins also go high impedence from the latch so an expansion card can access rom banks independently or does it always drive the bus?

The premise of the question, "so an expansion card can access ROM banks independently" is wrong.

A bus mastering card would not access ROM banks independently by replacing the ROM bank latch, it would access ROM banks independently by writing to the ROM latch at $0001. Ditto independent access to the HighRAM.

This is the way. The bank select pins are always driven by $01. Set $01 to change the currently selected bank. Just remember to preserve the value of $01 before writing to that address, or the system will crash when it returns from the DMA state.

Wavicle has actually been testing a modification to add vector pull logic, which zeroes the bank select register when an IRQ or NMI fires, and it definitely crashes the machine when the interrupt fires. The fix in that case is to re-write $01 with the value saved in RAM, af the end of the ISR, forcing the latch back into its previous state.

[spargue]

I appreciate this probably won't get implemented as it's most likely a large overhead in cost and resources. More surprised it wasn't a consideration. Wouldn't it have been better to join the rom ram latch outputs to the same bus so both ROM and RAM banks can be seen on the slot.

Capture2.JPG (74.98 KiB) Viewed 538471 times

As this is mixed in with the Hi_RAM and RAM CS lines it wouldn't have contention as only 1 would be active at a time.
With a bank Disable line (remove 1 IOx), the ram / rom banks can be forced high-Z and the slot can provide its own ram replacement bank. This would allow co-processors and other HW to have much larger ram access without having to go through a peephole interface and avoid a lot of copy code loops as the ram can be on a separate bus when it's not being mapped in.

[spargue]

Wavicle has actually been testing a modification to add vector pull logic, which zeroes the bank select register when an IRQ or NMI fires, and it definitely crashes the machine when the interrupt fires. The fix in that case is to re-write $01 with the value saved in RAM, af the end of the ISR, forcing the latch back into its previous state.

From how I've seen it done on the 65C816 you only need to worry about the low address bits to get the vector and can remap FFFF,E on vector Pull, Either by providing additional address bits from an encoder or forcing it to a new address via XOR bits as all other address lines are 1.
I think the biggest issue would be how to force the bank back after an ISR has returned. Perhaps an SR latch set on VPB and a way to trigger the reset via a trigger IO or instruction and then a set number of sync counts to get back to reasserting the bank latch.

I think all the dead instruction spaces map to a NOP now, so something like 0x42(nop / WDM on 65c816) would trigger the counter to re-enable the bank after the return instruction was done.
this was how the Z80 got around enabling interrupt eating up the stack from quick interrupts as EI would not take effect till after the next instruction usually a RETI