Expansion slots

[spargue]

Another thought I had on ROM / RAM banks being connected via bus mastering is the ram Banks can be joined by using A[0-12] with the ram bank on ROMB pins allowing a map of 8 / 32 banks of contiguous 64k when A[13-15] are held at b101.
What I'd really like is something like a 65C816 SuperCPU addon, but a lot of bottlenecks seem to be in the way

[TomXP411]

Another thought I had on ROM / RAM banks being connected via bus mastering is the ram Banks can be joined by using A[0-12] with the ram bank on ROMB pins allowing a map of 8 / 32 banks of contiguous 64k when A[13-15] are held at b101.
What I'd really like is something like a 65C816 SuperCPU addon, but a lot of bottlenecks seem to be in the way

A Super CPU style addon would ignore the X16's memory and have its own ROM and RAM. I'd probably also design it so that one of the banks (probably $FF) maps to the 65C02 bus, with ROM directly below that.

So when accessing any address in the FF:0000-FF:FFFF range, those go to the hardware on the X16 motherboard. When accessing from 00:0000 to FE:FFFF, the '816 would be talking to RAM or ROM on its own daughterboard.

There is no need to bank-switch the RAM or ROM banks, because a hypothetical 65C816 addon card would simply not need the 65C02 RAM or ROM. It would only need to access the 65C02 bus for I/O purposes.

[BruceRMcF]

If 8MB memory space on the card suffices, you can have any segment of $80 and above access the X16 main memory map, then when you latch the segment address, bit0 to bit6 can connect directly to the card memory bus A16 to A22 and bit7 selects between the card address space and the X16 address space.

[TomXP411]

If 8MB memory space on the card suffices, you can have any segment of $80 and above access the X16 main memory map, then when you latch the segment address, bit0 to bit6 can connect directly to the card memory bus A16 to A22 and bit7 selects between the card address space and the X16 address space.

Sure, but why? The original Super CPU could handle 16MB of RAM. I wouldn't settle for less if I was trying to create a Super CPU X16 Edition.

[spargue]

If 8MB memory space on the card suffices, you can have any segment of $80 and above access the X16 main memory map, then when you latch the segment address, bit0 to bit6 can connect directly to the card memory bus A16 to A22 and bit7 selects between the card address space and the X16 address space.

Sure, but why? The original Super CPU could handle 16MB of RAM. I wouldn't settle for less if I was trying to create a Super CPU X16 Edition.

It's possible to map the Whole banked ram + Rom into a continuous address space with a few minor gate changes on the system so it's accessible by an expansion card in master mode. You just need to make the latches go high-Z when the banks are not in use and be part of the BE high-Z state from the CPU. Shouldn't affect the main system bus too much as it's got all the same logic. I think it would really open up the system as a bus master doesn't have to go via the latches when it's using DMA.
Having a bank disable line would also allow IO and ram/rom to be dynamically remapped so a bank or section of a bank can become IO or Ram that can become decoupled.

[TomXP411]

It's possible to map the Whole banked ram + Rom into a continuous address space with a few minor gate changes on the system so it's accessible by an expansion card in master mode. You just need to make the latches go high-Z when the banks are not in use and be part of the BE high-Z state from the CPU. Shouldn't affect the main system bus too much as it's got all the same logic. I think it would really open up the system as a bus master doesn't have to go via the latches when it's using DMA.
Having a bank disable line would also allow IO and ram/rom to be dynamically remapped so a bank or section of a bank can become IO or Ram that can become decoupled.

Thing is... you're arguing this as if it's possible. It's not. The design is finished. PCBs are manufactured and being assembled as we speak.

We've already explained how the bank selection works, and how you can drive the bank select lines, by writing to $00 and $01. Anything else is just fantasy, and it's not relevant to this thread.

[spargue]

It is possible, but maybe not with the current design. A few minor mods would solve this and wouldn't break the current operation as it's still the same behavior under normal running. Guess you got it all 100% perfect the first time. No point in offering recommendations. Better tell Wavicle to not bother too; you've got this. I'd recommend you look at the revisions for the 'Spectrum Next project as they have been through several revisions and found ways to still be compatible and enhance the system.

Eagerly awaiting the EMC reports and design schematics...

[Ed Minchau]

They didn't get it 100% on the first try. The board has been through several revisions, and we're on revision 42 of the ROM.

But at some point you have to freeze the design for the programmers. Every revision causes breaking changes on non-trivial code. And perfection may be desirable, but there's a cost to everything, including time.

Also at some point product must move out the door, warts and all.

[DragWx]

I don't think it's productive to get angry that the X16's design doesn't simplify certain types of expansion cards and to berate people over it. What's more helpful is, engineering around the parameters that cannot change for now, and still coming up with a design for said expansion card, if you really want it to exist that is. There's definitely multiple ways to approach a DMA card, or a super CPU card, so nothing's out of reach just yet.

[spargue]

They didn't get it 100% on the first try. The board has been through several revisions, and we're on revision 42 of the ROM.

But at some point you have to freeze the design for the programmers. Every revision causes breaking changes on non-trivial code. And perfection may be desirable, but there's a cost to everything, including time.

Also at some point product must move out the door, warts and all.

The change I'm sugjesting won't break any code on the system, or change any of the expansion carts intended operation, but would allow a huge improvement in expansion cart flexibility and simplify how access is achieved. Currently a dma would need to co-operate with the cpu to access rom/ram banks. The change I'm sugjesting would allow full bus access to all banks.
This is equivalent to the C64 issue with loading from the tape causing slow operation due to the graphics chip needing extra cycles.
It can even be modded on existing pcbs if needed by adding a pcb patch to add the extra logic. Yes most people with the first 100 won't care too much, and I accept there's a hw technical debt both in time and funding.
I feel like the design team have just said no it's not our idea we couldn't be bothered to understand so please go away.