Expansion slots

[Martin Schmalenbach]

Just so I'm clear from having followed this interesting & spirited discussion...

If I WRITE to the banked ROM space for banks above #0-#31 and I have an expansion card with RAM mapped in to the ROM space, the data that is written by the CPU will actually be stored in the RAM, assuming I've wired the RAM up correctly?

The application I'm thinking of here is. simple Expansion card with RAM occupying several ROM banks at #32 and above that will be useful for speedier development of ROM-based code for cartridges etc.

Something like the circuit below/attached

Oh wait I just saw an issue. You need to watch A15 A14 from the slot to see if you are accessing the rom address space. Not (A15 & A14) - > #CE

Yes - I see that now - another good catch - thanks!!

[spargue]

On my PC now and not on my phone.
Noticed the WE doesn't use the PHI2 edge.
WE# needs to end slightly early to grab the data or it all collapses in a fuzzy way and you get bad writes.
OE doesn't need this latch as its grabbed from the CPU internally on PHY2
I'd recommend some inline resistors on the data lines 33R should be ok as it helps with noise and contention.

bank select.png (91.29 KiB) Viewed 361301 times

INPUTS to LED 1 & 2 gates can be connected to WE# OE# or CE2 pre gate to give the bank active read and write activities

[Martin Schmalenbach]

Thanks Spargue!

I’ve just sat down with a coffee and breakfast burrito at my local reservation breakfast shack to look at finalising this design when I saw your additional post here - much obliged. I hadn’t realised WE# needed to end a tad early so thanks for that.

One thing I’m not sufficiently clear on - the small triangles in your schematic - I take it these connect together to drive the LED activity and you didn’t draw those lines in for the purposes of clarity?

Cheers

Martin

[spargue]

Thanks Spargue!

I’ve just sat down with a coffee and breakfast burrito at my local reservation breakfast shack to look at finalising this design when I saw your additional post here - much obliged. I hadn’t realised WE# needed to end a tad early so thanks for that.

One thing I’m not sufficiently clear on - the small triangles in your schematic - I take it these connect together to drive the LED activity and you didn’t draw those lines in for the purposes of clarity?

Cheers

Martin

Wasn't sure if you wanted the LED for bank selection or for activity on the SRAM, Have uploaded it again with labels.
Just connect LED1 or 2 to WE, OE, BANK, or ROM to indicate when the system is writing, reading, or accessing the CART.

bank select.png (99.5 KiB) Viewed 361279 times

[Martin Schmalenbach]

Got it - thank you!!

I suspect I have just enough time to layout a PCB and get it manufactured and built before my X16 arrives from Texelec!

One last question, as seen from above, which is pin 1 on the expansion sockets?

[DragWx]

Pin 1 is top left on the expansion connector, when the PCB is right-side-up and front-towards-you (as in, i/o ports facing away from you). The pinout for the expansion connectors is also silkscreened on the backside of the PCB, once you receive it.

[mortarm]

...if a major problem came up. Like "halt and catch fire" major.

That was a good show.

[mgkaiser]

If I put an I2C device on an expansion card, do I need pull up resistors on SDA and SCL, or are they already in place on the bus?

[Wavicle]

If I put an I2C device on an expansion card, do I need pull up resistors on SDA and SCL, or are they already in place on the bus?

The I2C signals on the bus are on the same net as the I2C signals connected to the VIA. The pull-ups are already in place.

On the production board, this same net connects to the SMC. On the Dev board, there are jumpers between the host I2C and the SMC. On the OtterX, there are isolation transistors that separate the standby power domain from the main power domain.