Idea for cheap RAM

[neutrino]

On 10/21/2022 at 11:09 PM, Wavicle said:

The MOS 8726 had a 19-bit selection of REU address. It did not physically have enough pins to address more than that.

The MOS 8726 would either be piggybacked or replaced with another register level compatible to enable 16 MB operation.

On 10/21/2022 at 11:09 PM, Wavicle said:

What is the goal with more memory here?

Huge game environments, loading huge bitmap files etc.

On 10/21/2022 at 11:09 PM, Wavicle said:

Why couldn't a RAM expansion like this work like the REU and DMA from its local storage into X16 main memory?

It still needs to setup the DMA and then transfer the data from the "REU" to the main memory and then from there to whatever it's going to be used for. So more latency.

And by keeping the same method of access, coding would be more straightforward.

Better small pain upfront than long term chronic pain. Ie converting 10 programs right away or 1000 down the lane in regards to the register addresses.

 

[Wavicle]

On 10/21/2022 at 2:25 PM, neutrino said:

The MOS 8726 would either be piggybacked or replaced with another register level compatible to enable 16 MB operation.



Huge game environments, loading huge bitmap files etc.



It still needs to setup the DMA and then transfer the data from the "REU" to the main memory and then from there to whatever it's going to be used for. So more latency.



And by keeping the same method of access, coding would be more straightforward.



Better small pain upfront than long term chronic pain. Ie converting 10 programs right away or 1000 down the lane in regards to the register addresses.



 

You wouldn't piggyback in that case, you'd use a different component entirely.

What do you envision the address bus decoding and RAM bank latching circuit to look like in the base unit? Replacing the discrete logic with a high pin count CPLD "black box" isn't in keeping with the vision of the product.

[neutrino]

On 10/21/2022 at 11:56 PM, Wavicle said:

What do you envision the address bus decoding and RAM bank latching circuit to look like in the base unit?

Regarding the REU or the X16 ?

 

[Wavicle]

On 10/21/2022 at 3:01 PM, neutrino said:

Regarding the REU or the X16 ?



 

In the X16.

[neutrino]

Given the grainy video images and the design philosophy, I would guess some 7400-series latch + 7400-series support circuitry.

 

[Wavicle]

You would guess some 7400 series latches and support circuitry? I have four different revisions of my own design and an official proto 3 board in my office here with me. You can be specific.

I think you're looking at adding 5-6 ICs and potentially one level of logic decode which could put the propagation delay outside of what the memory needs to respond. For a feature that almost nobody would use. I appreciate your enthusiasm, but I don't see this as being practical without a CPLD doing the bus decode logic.

[mgkaiser]

You can add RAM on an expansion card. It will map into the ROM space between $c000 and $ffff, 16k pages. The easy way is to just use "ROM" pages 33-255 to add 3.5MB more of RAM. If you want more, also add an IO chip which will allow you to select from a larger chunk of RAM. Then you can add as much RAM as you like and use some combination for $01 and your custom IO to choose the page shown at $c000-$ffff.

[BruceRMcF]

You can add RAM on an expansion card. It will map into the ROM space between $c000 and $ffff, 16k pages. The easy way is to just use "ROM" pages 33-255 to add 3.5MB more of RAM. If you want more, also add an IO chip which will allow you to select from a larger chunk of RAM. Then you can add as much RAM as you like and use some combination for $01 and your custom IO to choose the page shown at $c000-$ffff.

Quite ... if you want daft amounts of RAM, and also ability to have both program code and data space in that RAM, allocate ROM page 255 to MegaRAM, slice the 16KB ROM window into two 8KB windows, have four 8bit tri-state latches in an I/O slot, two of the latches have A13-A28 for each window. I'm thinking that half a GB is enough RAM space.

An 8-1 NAND on the ROM bank inputs gives the MegaRAM slot, a 3-1 OR on /ROM select, /MegaRAM select, NOT(A13) selects the high bank address latch /OE, a 3-1 OR on /ROM select, /MegaRAM select, and A13 selects the low bank address latches /OE, a 3-1 OR on /ROM select, /MegaRAM select and NOT(PHI2) selects the MegaRAM. MegaRAM /RD is NOT(R/W), MegaRAM /WR is R/W ... so 2 full IC's and half of a hex inverter ... the selection is two gate delays on top of the /ROM gate delay.

So long as any 3.5MB ROMbank expansion doesn't populate the high 0.5MB, that MegaRAM can co-exist with the standard ROMbank expansion board.

[mgkaiser]

Since the design of the mainboard and the expansion slots are now locked in, we should be focusing on ideas you can implement on an expansion card.