Ed Minchau wrote: ↑Mon Feb 12, 2024 8:56 am
desertfish wrote: ↑Mon Feb 12, 2024 12:41 am
Updated the assembler with a new version that has the 4 "problematic" instructions removed (SMBx RMBx BBRx BBSx) due to the possibility of having a 65816 CPU in the X16, which doesn't have these instructions.
Benefit is also that the assembler shrunk quite significantly in size.
I've been programming almost exclusively in 65c02 assembly for the last four years, and my oh my are those commands useful for flags and semaphores. BBRx and BBSx give you a compare and branch in 5 cycles without using or affecting any flags or registers. SMBx and RMBx also each take only five cycles and don't affect flags or registers, whereas
LDA 2
ORA #$40
STA 2
is 8 cycles and can change Z.
Don't forget that the X16 has a 65C02, so the comparison there would be to the versions that are one cycle and two bytes shorter:
BBR #VERBOSE,FLAGS,LABEL ; using the alternate instruction format
LDA #VERBOSE
TRB FLAGS ; dirty bit set
BNE LABEL
...
-- or --
LDA #VERBOSE
TSB FLAGS ; dirty bit clear
BEQ LABEL
...
One thing I like about TRB and TSB is that it DOES affect the Z flag, so it can branch on either the bit starting out set or the bit starting out clear. Another thing is that it is such a simple progression from testing and setting/clearing the bit to or from testing without setting/clearing the bit, just swapping BIT for TRB/TSB.
However, I wouldn't leave BBR/BBS out -- rather, I'd use the alternate instruction format, since it is handier to share masks with BIT and BBR/BBS than to use a mask for BIT and a choice of opcode for BBR0-7/BBS0-7, and if feasible, I'd generate a warning that the resulting code is not compatible with 65816 Emulation mode.