File based Assembler

[desertfish]

Thanks for getting back to me. Yes, I'm using .byte just fine, but let's say I wanted to create 64 bytes, but I don't have values immediately to populate them with. I could .byte $00,$00,$00,$00,$00... 64, but I wanted to know if there was a way to use it to create 64 bytes (or any number) without having to populate them.

Thanks!

I've just updated the assembler with a new version that now supports ".fill" : You can use .fill <amount> or .fill <amount>,<value>

Also, there is a new "m" command that enters the machine language montior, for convenience. With 'g' you can exit back to the assembler.

[desertfish]

Updated the assembler with a new version that has the 4 "problematic" instructions removed (SMBx RMBx BBRx BBSx) due to the possibility of having a 65816 CPU in the X16, which doesn't have these instructions.
Benefit is also that the assembler shrunk quite significantly in size.

[Ed Minchau]

Updated the assembler with a new version that has the 4 "problematic" instructions removed (SMBx RMBx BBRx BBSx) due to the possibility of having a 65816 CPU in the X16, which doesn't have these instructions.
Benefit is also that the assembler shrunk quite significantly in size.

I've been programming almost exclusively in 65c02 assembly for the last four years, and my oh my are those commands useful for flags and semaphores. BBRx and BBSx give you a compare and branch in 5 cycles without using or affecting any flags or registers. SMBx and RMBx also each take only five cycles and don't affect flags or registers, whereas
LDA 2
ORA #$40
STA 2
is 8 cycles and can change Z.

[TomXP411]

Updated the assembler with a new version that has the 4 "problematic" instructions removed (SMBx RMBx BBRx BBSx) due to the possibility of having a 65816 CPU in the X16, which doesn't have these instructions.
Benefit is also that the assembler shrunk quite significantly in size.

I've been programming almost exclusively in 65c02 assembly for the last four years, and my oh my are those commands useful for flags and semaphores. BBRx and BBSx give you a compare and branch in 5 cycles without using or affecting any flags or registers. SMBx and RMBx also each take only five cycles and don't affect flags or registers, whereas
LDA 2
ORA #$40
STA 2
is 8 cycles and can change Z.

They are useful, but they are not compatible with 65816, so we are recommending people not use them - at least until eventual 65816 support is fully decided.

David is considering moving to the '816 for the Gen-2 system, and people are already buying and installing WDC65C816 CPUs for their Dev systems.

[Ed Minchau]

They are useful, but they are not compatible with 65816, so we are recommending people not use them - at least until eventual 65816 support is fully decided.

David is considering moving to the '816 for the Gen-2 system, and people are already buying and installing WDC65C816 CPUs for their Dev systems.

You know, after basing the entire system and all the software around the 65c02 for over four years now, switching the cpu at this late date should be a non-starter, for the same reason the "rev 1 post mortem" thread got shut down.

A computer with a 65c816 will not be a Commander X16. It would be a completely different computer, the Commander X816.

[kelli217]

You do remember why it's called the X16, right? While the A16-A23 demultiplexing issue caused it to fall by the wayside for a while, apparently David and Kevin have been keeping their options open since day one. Wavicle's early 'Community X16' board supported an 816, too; many of his old posts on the old forum and on Discord that were about doing breadboard testing of early designs for that board involved the 816.

Fulgen has also been hard at work creating a ROM that can handle the 816 being in native mode in the event of an interrupt while remaining transparent to 02 users.

[DragWx]

I was thinking about what this meant too, but I didn't want to comment in here because it's not quite on topic, so I'll be brief.

I think they just want the option of an upgrade path to the 65816 to stay available for those who would be interested in doing so, remembering that the X16 is meant for tinkering, and that includes seeing what can be done when a 65816 (a friend of the 6502, remember) is dropped in.

I don't think we'll be left in the dust if we choose to stick with the stock 65c02 the board ships with, so we should be safe to continue to develop for it. Even if there's a few people who want to swap it out with an '816, I don't think they're the majority of the userbase yet.

[desertfish]

For that reason I considered leaving the instructions in, but in the end I wanted to move forward with simplifying the tool and avoiding possible issues that might arise from using the instructions.

[BruceRMcF]

Updated the assembler with a new version that has the 4 "problematic" instructions removed (SMBx RMBx BBRx BBSx) due to the possibility of having a 65816 CPU in the X16, which doesn't have these instructions.
Benefit is also that the assembler shrunk quite significantly in size.

I've been programming almost exclusively in 65c02 assembly for the last four years, and my oh my are those commands useful for flags and semaphores. BBRx and BBSx give you a compare and branch in 5 cycles without using or affecting any flags or registers. SMBx and RMBx also each take only five cycles and don't affect flags or registers, whereas
LDA 2
ORA #$40
STA 2
is 8 cycles and can change Z.

Don't forget that the X16 has a 65C02, so the comparison there would be to the versions that are one cycle and two bytes shorter:

BBR #VERBOSE,FLAGS,LABEL ; using the alternate instruction format

LDA #VERBOSE
TRB FLAGS ; dirty bit set
BNE LABEL
...
-- or --
LDA #VERBOSE
TSB FLAGS ; dirty bit clear
BEQ LABEL
...

One thing I like about TRB and TSB is that it DOES affect the Z flag, so it can branch on either the bit starting out set or the bit starting out clear. Another thing is that it is such a simple progression from testing and setting/clearing the bit to or from testing without setting/clearing the bit, just swapping BIT for TRB/TSB.

However, I wouldn't leave BBR/BBS out -- rather, I'd use the alternate instruction format, since it is handier to share masks with BIT and BBR/BBS than to use a mask for BIT and a choice of opcode for BBR0-7/BBS0-7, and if feasible, I'd generate a warning that the resulting code is not compatible with 65816 Emulation mode.

[Edmond D]

A computer with a 65c816 will not be a Commander X16. It would be a completely different computer, the Commander X816.

How about a Super X16, much like the Super PET, power down, flick a switch and then wake up on a "new" expanded platform.