Not to ask silly questions, but is there a timing graph for the component you're using, and do you know whether your clock input is conforming to the latch's requirements?
Not silly at all as I am completely new to this and that hadn't occurred to me. Shall have a look thanks ?
In theory, it should work. I have just tested in Logisim as well, both the buil-in d-latch and one made from NAND gates seems to be able to divide the clock signal.
As StephenHorn says, ensure that your chip(s) can handle the signal they receive. (dig in to the datasheets).
I built with NOR and AND as in the Ben Eater videos. Will try this one as well ?
The 74ls74 seems to be edge triggered without using the strange NOT-NOT-NOT-AND circuit I have above.
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Simple D-type divide by 2 circuits have problems if the clock edges are not sharp enough. Feeding the clock through an inverter might sharpen its edges.
Simple D-type divide by 2 circuits have problems if the clock edges are not sharp enough. Feeding the clock through an inverter might sharpen its edges.
thanks, will give all of these a try once manage to free up some time ?
Holy smokes, no wonder your latch was having problems. That original signal isn't a square wave clock signal--- it's a bleedin' triangle wave! Was that really the output from a crystal oscillator?
Edit: I may be dumb or simply inexperienced, I thought crystal oscillators produced square-ish signals.
Interestingly enough, if I put even a 6Mhz, or faster, crystal in instead, it doesn't work very well at all. I was lucky that I found a tutorial using components that matches the speeds I wanted to run I guess. There certainly is lots to learn here ?