YM2151 questions

[luke@platypuscreations.net]

Good evening folks,

I've been researching the YM2151 chip and I have couple questions.

First, it appears this chip only has a digital output and I'm curious how the X16 is handling the digital to analog conversion.  From the docs I've read, Yamaha typically paired this with a YM3012, but I didn't know if that was how the X16 is doing it.

Second, I know one of the goals of the X16 is to use readily available parts but I'm having trouble sourcing this chip anywhere besides eBay. I'm just curious where folks are sourcing these chips.

--Luke

[Lorin Millsap]

Good evening folks,
I've been researching the YM2151 chip and I have couple questions.
First, it appears this chip only has a digital output and I'm curious how the X16 is handling the digital to analog conversion.  From the docs I've read, Yamaha typically paired this with a YM3012, but I didn't know if that was how the X16 is doing it.
Second, I know one of the goals of the X16 is to use readily available parts but I'm having trouble sourcing this chip anywhere besides eBay. I'm just curious where folks are sourcing these chips.
--Luke

These chips are readily available through our supply channels.

This chip was an exception because firstly it met our cost goals and secondly developing an open source FPGA core if the supply dries up isn’t a problem.

Yes it is paired with the YM3012.


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[luke@platypuscreations.net]

1 minute ago, Lorin Millsap said:

These chips are readily available through our supply channels.



This chip was an exception because firstly it met our cost goals and secondly developing an open source FPGA core if the supply dries up isn’t a problem.



Yes it is paired with the YM3012.





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Oh cool, thanks for the details and the quick response!

[m00dawg]

On 1/14/2021 at 9:29 PM, Lorin Millsap said:

This chip was an exception because firstly it met our cost goals and secondly developing an open source FPGA core if the supply dries up isn’t a problem.

Is there a plan on how the FPGA would be implemented on the final board rev? On revisions 1 and 2, the YM chips socket right onto the board, but an FPGA solution would have to piggyback on both those sockets? Has any thought been given to that and/or using a stackable daughterboard (ala VERA) and just a pin header (or even just putting it on a card)? Or will that just be a future motherboard revision down the road?

It's been on my mind for days haha and I shouldn't worry about it that much given the availability of the chips, but was wondering if there were plans for this eventuality.

[Guybrush]

1 hour ago, m00dawg said:

Is there a plan on how the FPGA would be implemented on the final board rev? On revisions 1 and 2, the YM chips socket right onto the board, but an FPGA solution would have to piggyback on both those sockets? Has any thought been given to that and/or using a stackable daughterboard (ala VERA) and just a pin header (or even just putting it on a card)? Or will that just be a future motherboard revision down the road?

I believe the idea is to use a beefier FPGA to run all (most?) of the chips... CPU, VERA, VIAs, YM, address decoding logic, the whole shebang. That would leave only RAM, ROM and perhaps some glue logic as separate physical chips.

[m00dawg]

1 minute ago, Guybrush said:

I believe the idea is to use a beefier FPGA to run all (most?) of the chips... CPU, VERA, VIAs, YM, address decoding logic, the whole shebang. That would leave only RAM, ROM and perhaps some glue logic as separate physical chips.

That's for the "stage 2" motherboard I thought? And stage 3 is the Pi like design (which is likely to replace as many external chips with a single FPGA as possible for size and costs). The stage 1 board, I thought, was meant to be the most expandable/moddable with as many off the shelf chips as possible. Which means, today, real YM2151 chips because they're available. My wonder was if the final revision of the stage 1 board might account for the eventuality of needing an FPGA solution and making that compatible without having to do any hacks.

There's a lot of options potentially. Including I suppose not worrying about it for Stage 1 until it becomes a problem - in which case one might be able to come up with a Ms. Pac-Man style add on card that plugs into the existing sockets directly or via ribbon cables. Given the memory map of the YM2151 it sure seems like it could also be an expansion card (though that'd eat up a slot, require more modifications to the kernel, and might be more expensive). I rather like the idea of card myself though a VERA style riser that just connects via a pin header would make things nice and tidy too.

Curiosity killed the cat I guess ? I'm sure we'll find out eventually, though hoping the team does address this in a future update/video perhaps.

[BruceMcF]

2 hours ago, m00dawg said:

That's for the "stage 2" motherboard I thought? And stage 3 is the Pi like design (which is likely to replace as many external chips with a single FPGA as possible for size and costs). The stage 1 board, I thought, was meant to be the most expandable/moddable with as many off the shelf chips as possible. Which means, today, real YM2151 chips because they're available. My wonder was if the final revision of the stage 1 board might account for the eventuality of needing an FPGA solution and making that compatible without having to do any hacks.



There's a lot of options potentially. Including I suppose not worrying about it for Stage 1 until it becomes a problem - in which case one might be able to come up with a Ms. Pac-Man style add on card that plugs into the existing sockets directly or via ribbon cables. Given the memory map of the YM2151 it sure seems like it could also be an expansion card (though that'd eat up a slot, require more modifications to the kernel, and might be more expensive). I rather like the idea of card myself though a VERA style riser that just connects via a pin header would make things nice and tidy too.



Curiosity killed the cat I guess ? I'm sure we'll find out eventually, though hoping the team does address this in a future update/video perhaps.

That's the stage 3 that might include CPU and VIA cores (which are available under license from WDC) and all of the glue logic together with Vera in a single beefier FPGA, but the stage 2 is surface mount with cost reductions, which could include a CPLD/FPGA for the glue logic or a beefier FPGA to include it with Vera.

An FPGA might handle the YM2151 in either stage3 or both stage2 and 3, with the real stock for the through pin reference design.

 

[Lorin Millsap]

If the YM2151 becomes unavailable it would be replaced with an FPGA on a daughter card with pin headers to plug into a dip socket. But we are only crossing that bridge if it becomes necessary.


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[kliepatsch]

I am trying to figure out how to use the YM 2151. I have looked at how @SlithyMatt does it in ChaseVault. I found that he uses the addresses $9FE0 for the register byte and $9FE1 as the data byte for communication with the YM 2151. However, in the official documentation, this area is denoted as "Future expansion"

https://github.com/commanderx16/x16-docs/blob/master/Commander X16 Programmer's Reference Guide.md#io-area

Are there any official sources or did the few people who have actually used the YM 2151 so far figure this out by themselves?

[Elektron72]

Although YM2151 support is in the emulator (if you go to line 112 of memory.c, you will see these addresses connected to the YM2151 emulation), it is not currently documented, and these addresses may change in the future. I am assuming that they will document the YM2151 addresses after they finish working on the next hardware revision.