Hi again! I've been working for quite awhile to get the new layout complete, and I think we are just about ready to run the second prototype! There are quite a number of changes to this board over the previous version, so I do expect a few, ahem, challenges perhaps??That said, a lot of time has been spent testing on breadboards and optimizing so I think we should be close to the final specs on this system. As mentioned, there are code breaking changes with the system. I will post more for the devs out there in a post below. The VERA has also changed quite a bit. Namely, it now has 32 registers, but I'll let @Frank van den Hoeftalk more about that when he is ready to post some updates. Also, I made two proto boards to test the bus and get the alignment right for the final design. Progress is being made, thanks for everyone's patience and have a great day!
Dude this is thrilling to see! I saw your post on Facebook first and figured I'd poke over here a bit. I did want to know if those prototyping boards were going to be shipped with the system as a bundle or sold separately. If it was considered to be bundled with it, would it just be the S boards? Also, what would the prices beif you decided to sell them?
This is so much better than reading the same post on FB ?
Visit my Github repo
or my personal site with CX16/C64/6502 related information.
Feel free to contact me regarding any of my projects or even about meeting up somewhere near Denmark
This is so much better than reading the same post on FB ?
Agreed! In future we'll try to only make announcement posts here, then paste the link into FB (which will generate a preview of the post anyway). The website will be the go-to #1 source.
@Kevin Williams I'm having a hard time finding User Port info on the FB group. I recall you had planned to make it Centronics compatible. Could you refresh my memory here about the User port pinout? I'm trying to figure out how many pins we'll have available for GPIO.
? That said, a lot of time has been spent testing on breadboards and optimizing so I think we should be close to the final specs on this system. As mentioned, there are code breaking changes with the system. I will post more for the devs out there in a post below. The VERA has also changed quite a bit. Namely, it now has 32 registers, but I'll let @Frank van den Hoef talk more about that when he is ready to post some updates. Also, I made two proto boards to test the bus and get the alignment right for the final design. Progress is being made, thanks for everyone's patience and have a great day!
