Addressing logic

Perifractic · Post by **Perifractic** » Sat Mar 06, 2021 1:43 am

I definitely like those changes, it's a lot more comprehensive. None of it is updated in the wiki.

What Wiki is that?

Perifractic, X16 Visual Designer
http://youtube.com/perifractic

RTKimz · Post by **RTKimz** » Sat Mar 06, 2021 2:40 am

54 minutes ago, Perifractic said:

What Wiki is that?

Perifractic, X16 Visual Designer

http://youtube.com/perifractic

As far as I can tell jbaum81 is referring to this website ( http://wilsonminesco.com/6502primer/ )

It isn't exactly a wiki but it does contain a lot of reference material that I have come to expect out of a wikis.

Perifractic · Post by **Perifractic** » Sat Mar 06, 2021 3:59 am

As far as I can tell jbaum81 is referring to this website ( http://wilsonminesco.com/6502primer/ )
It isn't exactly a wiki but it does contain a lot of reference material that I have come to expect out of a wikis.

Ah, okay that isn’t an official resource, just to be clear then.

Perifractic, X16 Visual Designer
http://youtube.com/perifractic

BruceMcF · Post by **BruceMcF** » Sat Mar 06, 2021 6:04 am

14 hours ago, jbaum81 said:

I think I follow, but what have you gained by first splitting the upper 32k out? If we acknowledge that a1-14 still have to be evaluated?

The latches I've chosen require OE to be off when latching, the logic I came up with there was AND the clock pulse with write and the logic that addresses the chip then invert OE as I bring the cp high. Not in that exact order of course, I do bring OE high well before CP going high. I attached my diagram above if your interested.

With something like a 74xx373, you may be able to tie /OE to ground, because the latch outputs are tied to address lines on chips that won't be selected when LE is high on the bank register latches. That is, just because you have a tri-state latch doesn't mean tri-state is necessarily required in this case.

Evaluating A1-A15=0 can be done with two chips in one level logic ... two dual 4-input OR gates would be cleaner if they can be had ... though come to think of it, that should be A1-A15=R/W=0, which uses up all 16 inputs. If that is fast enough logic to be set up in one logic level before PHI2=1, then you can use PHI2 and A0 as the input into an active high 2x4 demux selected on A1-A15=R/W=0, with $0, $1 not connected and $2 and $3 as LE for the $0000 and $0001 latch, respectively.

It is entirely independent of the rest of the chip selects, so none of the other chip selects have to wait on the outcome of the latch logic.

picosecond · Post by **picosecond** » Sat Mar 06, 2021 12:54 pm

19 hours ago, jbaum81 said:

I'd definitely prefer to just tie it to ground though if the output will literally just echo the state of the flipflops as they change. Here is the datasheet for the latch I chose.

https://www.ti.com/lit/ds/symlink/sn74f574.pdf

Geez, where is my head? Bank registers need to be initialized at power on. That is easiest using a resettable flop, like the '273.

jbaum81 · Post by **jbaum81** » Sat Mar 06, 2021 3:43 pm

I think I found my solution!!!

Using some 8 bit comparators. All logic is >= 10ns at each phase.

I think my only gap here is the flip-flop for the rom. I think I need to hold OE high with some pull down resistors on it's outputs to keep the rom on bank 0 for boot. Was thinking maybe a 555 timer tied to the yet to be created reset circuit.... The thought would be to hold RST low during power on with some additional logic to keep OE high long enough to execute an instruction to latch it at 00. Anyone have a better idea for boot?

Lorin Millsap · Post by **Lorin Millsap** » Sat Mar 06, 2021 4:10 pm

So question. Not against people learning, but why are you attempting to clone a product we haven’t released yet?

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picosecond · Post by **picosecond** » Sat Mar 06, 2021 4:20 pm

24 minutes ago, jbaum81 said:

Anyone have a better idea for boot?

Replace the '574 with '273, and use its built-in clear function.

Be careful mixing logic families. 'AC11032 VIH is not compatible with 'F521 VOH.

You can replace all of the jelly bean logic used to generate both bank register clocks with a single '138, similar to BruceMcF's comment above.

jbaum81 · Post by **jbaum81** » Sat Mar 06, 2021 4:42 pm

17 minutes ago, Lorin Millsap said:

So question. Not against people learning, but why are you attempting to clone a product we haven’t released yet?

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I started this adventure to build my own 6502 computer inspired by Ben Eater's video's. After I did that and wrote a little assembly I sort of decided that I didn't want to be on an island by myself and decided I'd maintain compatibility with the CX16. This way I get the experience of designing my own circuits (Note I have not asked for yours), and mine would be compatible with your software. To be clear I absolutely 1000000000% plan on supporting this project and will purchase a CX16 once released, but ultimately would like to run my own board that way I'm familiar with the hardware and able to support it myself. Soldering chips to someone else's design doesn't quite tickle my fancy lol. Also I did email David about this, not necessarily to ask permission, but he is aware of what I'm up to and didn't take any issue with it. If I'm oversharing or offending anyone on the project please let me know, obviously my interest isn't to 'clone' it in any way to undermine or hurt the project.

Quote

14 hours ago, Perifractic said:

What Wiki is that?

Perifractic, X16 Visual Designer

http://youtube.com/perifractic

Apologies, I was actually referencing the programming guide on GitHub, sorry for the confusion.

19 minutes ago, picosecond said:

Replace the '574 with '273, and use its built-in clear function.

Be careful mixing logic families. 'AC11032 VIH is not compatible with 'F521 VOH.

You can replace all of the jelly bean logic used to generate both bank register clocks with a single '138, similar to BruceMcF's comment above.

As for mixing logic, are you referencing the differences between TTL and CMOS? Most I could find on those is the voltages considered high/low, which, as far as I understand, shouldn't really make any difference in my logic? Can you clarify or point me in the right direction as to what makes them incompatible?

Thanks for the pointers, I'll check into that.

picosecond · Post by **picosecond** » Sat Mar 06, 2021 6:13 pm

35 minutes ago, jbaum81 said:

are you referencing the differences between TTL and CMOS? Can you clarify or point me in the right direction as to what makes them incompatible?

Yes, TTL and CMOS have different specifications for low and high voltage levels. Let's assume a minimum VCC of 4.5V for this example.

For the F521, a "1" at the output means a voltage greater than 2.5V. This is the VOH(min) parameter in the datasheet.

For the AC11032, a "1" at the input is guaranteed to be recognized only if the voltage is 3.15V or greater. This is the VIH(min) parameter in the datasheet.

So a perfectly valid "1" for the F521 could be wrongly interpreted as a "0" by the AC11032. Obviously that would be bad. If you ever wondered why there are both AC and ACT logic families this is the reason. ACT input voltage thresholds are shifted downwards to be compatible with TTL output voltages.

This article has a more complete explanation: https://www.allaboutcircuits.com/textbook/digital/chpt-3/logic-signal-voltage-levels/

As an aside, in your last schematic you could connect RW to that unused 'F521 input and save some glue logic.