It’s a shame PS2 sends 11 bits because the VIA has built-in shift register functionality, but only 8 bits wide. The VIA could shift in the PS2 data automatically and the kernel could just read the latched value at leisure.
But not only are there too many bits, there are also too many bytes... maybe VIA could pause the PS2 device between each byte but the problem remains that the parity and stop bits will push the 2 MSB of the keycode out of the latch.
now, the joysticks don’t have this problem. THEY return 8 bits per latch (rather 16 but that’s just two runs of shifting in 8 bits) However, I bet the clock/latch pins of the controller ports aren’t connected to the correct pins of the VIA to do this in HW.
If this is the case, understandably, they’re not going to redesign the board to leverage this.
now I’m curious and gonna go look that up... lol
Update:
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I bet the clock/latch pins of the controller ports aren’t connected to the correct pins of the VIA to do this in HW.
Confirmed - the emulator's via.h specifies that the DATA pins of the controllers 0..4 are connected to VIA1:PA7..PA4, and the common latch/clock pins are driven by PA2 and PA3, respectively.
The shift register uses CB1 and CB2. Using these, it would've been possible to do hardware-accelerated joystick polling, but it would've limited the system to using one joystick per VIA, and would still have required one data pin to be an output for sending latch commands to the controllers. Using SR mode 2, the VIA would shift in 8 bits from the controller every time you read from the shift register. Mode 2 means shift one bit each clock cycle, and stop after shifting 8 bits. So in this regime, you can assume the latch holds the previous value shifted in (except for the very first time, which could be done once during system init to seed this). You would just read from the latch however many bytes you want from the controller, and prior to reading the last byte (every byte for NES, every other byte for SNES), you would set and clear the latch pin so the final read will simultaneously trigger the VIA to shift in the first byte of this latching.