Commander X16

My recommendation would be - don't make a Neanderthal X16. Make a Neanderthal something else that uses similar parts. There are a few things about the X16 that make it tougher than it first appears. There's a reason I and the two others I know of who have made X16-like prototypes have all used SPLDs for one or both of address decoding and memory banking. Getting the X16 KERNAL up on a non-X16 device is probably a massively more complex task than you may think. Without VERA, you will never have an X16 anyway and you will still need something to provide you with video and storage.

Wavicle, you're right, what I was thinking of isn't really an X16.  It's just a "Commander" of some kind.

And, you're also right about the KERNAL.  It might well have to be written from scratch, and that sounds just painful.

 

6 hours ago, BruceMcF said:

As in,

1. 
   6.25 MHz?
   


2. 
   I/O page at $C000-$C0FF overlaying the bottom page
   


3. 
   of the 16K ROM window,
   


4. 
   a single 512K RAM
   


5. 
   and a 64K RAM
   


6. 
   with the bottom 32K of Low RAM locked at $0000-$7FFFF,
   


7. 
   an 8K window at $8000-$9FFF
   


8. 
   and another at $A000-$BFFF,
   


9. 
   the high window six bits of banks over the full range of 512K,
   


10. 
    the low window two bits of four 8K banks for the other 32K of Low RAM?
    

Ah, so you're leading the witness.  Yes, I'll bite -- it sounds in the spirit of X16, sans VERA.  What is it?  What's the CPU?  (The Gigatron runs at 6.25 MHz....)

 

9 minutes ago, rje said:

Wavicle, you're right, what I was thinking of isn't really an X16.  It's just a "Commander" of some kind.



And, you're also right about the KERNAL.  It might well have to be written from scratch, and that sounds just painful.

If it's an amateur project, then a lot of people would start with the C64 KERNAL and modify it from there. In part, because the specific project would not be a lot of people.

11 hours ago, rje said:

Ah, so you're leading the witness.  Yes, I'll bite -- it sounds in the spirit of X16, sans VERA.  What is it?  What's the CPU?  (The Gigatron runs at 6.25 MHz....)

Either the 65C02 or the 65816 running like a 65802. It's just the Y16 ... the basic X16 approach, but a set of slightly different design decisions that have been proposed along the way.

And plus different simplifications ... exactly 512K extended memory, no mouse, only a control pad and PS/2 keyboard, etc.

I reckon it's just a thought experiment, but since Vera with all of it's nifty features exists, so people who need a bitmap can go there to get one, I'd look into porting the original Gameduino to a new FPGA family, shift it to a more standard 640x480 VGA display mode, strip out the sound generators, and give it an SPI (master) port that the J1 coprocessor can run. With a system clock synchronous with the Gameduino external clock (why 6.25MHz = 25MHz/4), designing the 6502 bus interface so that there is no contention with the J1 should be a lot simpler.

 

Hmm now I have a picture in my mind of an RC2014 Classic II-like backplane/buss thing with X16 cards plugged in... including the VERA card... and using SPLDs or CPLDs...

 

On 8/19/2021 at 8:33 PM, rje said:

I could probably get a 65C02 connected to the KERNAL (on EEPROM) and a static RAM.

It would probably work and not be tooo hard. But begin with a really low frequency 100 - 1000 kHz. In fact it's possible to use just CPU + SRAM with some "boot" bus interfacing.

If you add a programmable peripheral interface like MOS 6522/6526 or Intel 8255 you could control real other things. IoT the way it used to be. Even a latch from the 7400-series of chip can provide I/O. Enabling IoT without the modern complications.

Though when dealing with electronics beware of:

 * Frequencies above ~20 MHz tend to force the designer to pay attention to electrical integrity.

 * Ground.. more ground and then shield. Or the signal gets lost in translation..

 * Each IC should have a physically nearby capacitor to provide power during short switch times.

 * The power source should be stabilized with capacitors of different values to ensure all surge time windows are all covered. (ESR etc..)

 * Switched power supplies can look good with a multi-meter but inject too much ripple.

 * Sold joints should look smooth and nice because they also tend to be nice for high frequency signals.

 * Avoid long conductors on PCB or otherwise that don't have a proper ground path or (capacitance) stabilization.

 * Connect all unused inputs to ground or "+" via 10 kohm resistor or similar.

 * Electronics involving signals without an oscilloscope is like driving a car without eyes.

 

6502 is doable on a breadboard:

https://invidious.rhyshl.live/watch?v=tcIiftdNAMU - Rahul Kar: Homebrew 6502 single board computer on a breadboard - Hello world! (2020-11-14)

https://invidious.rhyshl.live/watch?v=_mBuQOuDVf8 - LateBlt: Let's make a simple 6502-Based computer, Part 1: The CPU and clock circuit (2020-09-21)

  Neat tip by "Dave H": "A little more detail on the start up of the 6502 >>> The reset vector is at $FFFC/$FFFD, that's where the 6502 starts (it's expecting a ROM to be at that address). It obtains two bytes from those locations and jumps to that address. If you feed a NOP instruction ($EA) into the data bus when the 6502 is attempting to read the reset vector address, it will fetch and jump to address $EAEA and start executing code from there . The code being executed will be the NOP ($EA) that is being feed into the data bus. Once the code execution reaches $FFFF only then will it wrap around to $0000"

https://invidious.rhyshl.live/watch?v=VXHhoFANhg4 - LateBlt: Let's make a simple 6502-Based computer, Part 3: A different clock circuit, And adding the i/O chip (2020-10-26)

1:06:18 Shows when a 6502 + ROM + I/O  with LEDs are powered on.

https://yewtu.be/channel/UCS0N5baNlQWJCUrhCEo8WlA - channel: Ben Eater

  Good info on various electronics devices. (RS-232, SPI, USB, PS/2, CRC, bus timing)

Here's a simple setup with CPU + parallel I/O + Serial + ROM/RAM Dallas DS1230Y 32k x 8:

https://invidious.rhyshl.live/watch?v=Sbk92is3u5U - Voyageur: 6502 SBC with one single chip for ROM and RAM (2021-10-02)

  0:24 General overview of chips.

  0:28 "OSI 6502 BASIC version 1.0 rev 3.2 copyright 1977 by Microsoft Co."

  1:36 Testrun with LED.

https://datasheets.maximintegrated.com/en/ds/DS1230AB-DS1230Y.pdf

  "The DS1230 256k Nonvolatile SRAMs are 262,144-bit, fully static, nonvolatile SRAMs organized as 32,768 words by 8 bits. Each NV SRAM has a self-contained lithium energy source"

Walkthrough of the WDC 65C02 CPU pins:

https://invidious.rhyshl.live/watch?v=9KwaLIUvtRU - XTronical: Building a 6502 computer: Episode 2, The pins of the 6502 and connecting for a basic system. (2022-02-19)

 

My tip: Get a breadboard, jumper wires, 6502, oscillator, ROM, RAM, parallel I/O (6526), cheap 2nd hand oscilloscope. Then try. You could even use a 555 chip to produce a really slow clock to avoid 99% of the EMI issues in the beginning.

There's a microcontroller (MCU) called "Intel 8051" and compatibles (8031) which is real shit but it's commonly used where a cheap and simple controller is needed. Too bad there was no 6502 equivalent.

AVR huh.. Now where's my single chip 6502! ..? ?

 

An X16-compatible computer on a breadboard is doable -- even at 8MHz. I wouldn't recommend it to anyone without a lot of experience debugging signal integrity issues. Back in April I had an essentially complete X16 compatible computer on a few breadboards.

@Wavicle I wouldn't mind a separate thread with some more pictures and explanation on how it worked ?

How much power did it use?