Re: Version 1 Postmortem & Proposal for future
Posted: Thu Feb 08, 2024 8:20 pm
First things first: everybody stop beating up on arachnivore. How we integrate new-comers into the community is an important component of being a healthy community. When possible criticize ideas, not individuals.
The two are very different. VERA cannot produce the same sort of FM audio that the YM2151 produces. The FM-synthesized audio is very characteristic of high-end retro audio and in my opinion adds to the feeling of "quality" of the product. My opinion isn't shared by all, and I understand that reasonable people can disagree on this point.
If one is willing to assemble it yourself, there is a $250 kit available also: https://www.vectorheadarcade.com/produc ... mputer-kitarachnivore wrote: ↑Thu Feb 08, 2024 12:51 am I'm sure some of those requirements have shifted over time, and it looks like the project has managed to garner a bit of a community. Still, one of the most glaring problems with the current version is that it ended up with a $350 price tag, which puts it well north of a MiSTER system which can essentially emulate the X16 along with many other systems.
There has been ongoing discussion about the future of the YM2151. One argument put forth is that VERA audio is good enough.arachnivore wrote: ↑Thu Feb 08, 2024 12:51 am Obviously, the no FPGA rule was eventually dropped, but I don't think the potential of the FPGA was fully realized. For example, as far as I understand, the VERA board is capable of implementing a sound chip making the Yamaha chip a bit redundant.
The two are very different. VERA cannot produce the same sort of FM audio that the YM2151 produces. The FM-synthesized audio is very characteristic of high-end retro audio and in my opinion adds to the feeling of "quality" of the product. My opinion isn't shared by all, and I understand that reasonable people can disagree on this point.
The kit above does not ship with a YM2151 but instead uses an FPGA-based drop-in replacement. This idea is not anathema within the community. I believe jumping from BASIC to HDL is a little extreme though. What the X16 does bring to the table is a very simple bus design that can be implemented in a handful of logic gates. On the kit version, the individual blocks implemented with the gates are highlighted.arachnivore wrote: ↑Thu Feb 08, 2024 12:51 am The thing about FPGAs is: They shouldn’t require any deeper understanding, however; they do allow for a deeper understanding of the system. I could put an FPGA with a config ROM and voltage regulator on a PCB with 40 through-hole pins and cover the whole thing with black plastic and you wouldn't even know it's not an authentic 6502 or whatever. However, I could also expose the config ROM so that onece the user learns BASIC then assembly, they can move on to HDL if they want to. It lets them go further down the rabbit hole, but it doesn't force them to.
I'm not quite sure what the point here is. Is a change to the CPU to one that is more FPGA-friendly being proposed?arachnivore wrote: ↑Thu Feb 08, 2024 12:51 am Here are some nubers:
A 6502 core takes up <700 logic elements running over 10 MHz (source)
A 32-bit RISC-V core (a more relevant architecture to learn) can use about 900 logic elements running several hundred MHz (source)
Some crazy people have even managed to squeeze a RISC-V CPU down to <200 Logic elements.
The 6502 is actually pretty hard to implement effeiciently in an FPGA. Other 8-bit designs from Lattice, Xilinx, and Intel use in the 200 Logic element range and run in the 50+ MHz range even on low end hardware.
An FPGA-based low-cost system is roughly what is already planned. Swapping the CPU out is not. Replacing the CPU with a modern 32-bit replacement is about as far from the retro aesthetic being sought as one could get. There may be better languages than BASIC, but I think it is important to keep in mind that these old machines did not require one to become intimately familiar with filesystems and file management prior to pounding out code. There aren't many languages that are friendly towards that model. As infuriating as BASIC line numbers are/were, they facilitated this objective.arachnivore wrote: ↑Thu Feb 08, 2024 12:51 am Anyway, a single FPGA replacing all that logic is 100% the way to go. I think a RISC-V CPU would make more sense than a 6502. I also think there might be better languages than BASIC to start out with, but I haven't really done a survey.