Commander X16

Thank you! Much appreciated.

If for some reason, the down-clocking of the LFSR is too difficult to implement, here's another way of decorrelating subsequent iterations:

We could cut the sequence of 65535 values short somehow, which makes the total number of samples less similar to a multiple of 512.
E.g. we could reset the LFSR content to $FFFF when the current value is equal to the one that comes N iterations before $FFFF would occur naturally, with N something of the order of 10 or 20 maybe.

Or the other way around: when the LFSR content reaches $FFFF, we set its content to the value that would occur naturally 10 or 20 iterations after $FFFF.

Let's hope it is as easy as you suggest.

I wouldn't expect there to be any problems with changing how the LFSR is clocked, because, in terms of circuitry, it'd just be changing what signal drives the CLK input of the shifter, and I think the signal exists already because it's used to sequence channel updates.

Nevertheless, if this change were implemented, I'd greatly appreciate it and it would be the thing that makes me (finally) update my hardware away from r47.