1 hour ago, BruceMcF said:
The design of the board he describes seems to be using a CPLD or FPGA for that, at least by the time that "memory map version 1" was dropped for the simpler "memory map version 2".
Of course, at the time, as at present, they were not talking about what was going on in detail, but they were at least referring to issues with bus timing, and that would as easily be a timing issue rather than a complexity issue ... the in production, through pin static RAM they are using has pretty tight timing for chip select partway through an 8MHz clock cycle, and pulling the chip select logic into a single PLD speeds up the timing of the assert. To put the chip selects and A16-A23 out through a single PLD requires more than the 10 output pins available on a 22V10, hence a CPLD or as part of the functions on an FPGA.
(In the Feonix256, that's done through a bus master FPGA, which AFAIR in the latest design has been integrated with the audio master FPGA.)
I think they are going to have a lot of difficulty pulling off 8MHz, even exploiting early address bus stabilization, if the parts shown in the videos are correct (xx74ACTxx logic, Alliance AS6C4008 SRAM). With tACC=70ns on the CPU and tACE=55ns on the SRAM, there may only be 15ns available from address stable until the correct CS# must be asserted. Those gates have a propagation delay up to 9.5ns, therefore if your output requires more than 1 level of combinatorial logic (which I think is guaranteed to be the case for memory below $9F00), you have the potential to hit a timing violation. Switching to faster xx74AHCTxx components will let you have two levels of logic
if your load capacitance and temperature are sufficiently low (i.e. 15 pF and 25C or better). If I recall correctly, the problem with the v2 prototype board was that CS and PHI2 were effectively being ANDed together which should never work at 8MHz because you have less than 55ns from PHI2 until the end of tACC.
A16-A23 should not need to go
through a PLD unless it is also demuxing the data bus, which is quite a bit more expensive than using a 74AHCT245 and only 1ns faster. In my experimental case, I only feed the high address bits into the SPLD and only the chip select signals come out.
Incidentally, the SPLD has a propagation delay as low as 7ns so you could go through two of them without a timing violation at 8Mhz on a 65C02. I'm not expert working with these old parts, but going strictly by the numbers, I just don't see how CX16 is going to be able to run stable at 8MHz unless the published timing values are all lies. If they do manage it, I am probably going to buy a sacrificial unit just to connect to the logic analyzer and figure out HOW. At 4MHz, all of this concern goes away and delay for demuxing the data bus is not going to be fatal to a 65C816.