6 hours ago, peapod said:
Have now. Completely missed it first time round sorry.
P is what is being prototyped at the moment, phase 1
C is the mini itx version in phase 2
E is the raspberry pi size one in phase 3
Old person brain here, didn't join the dots at first glance.
Ta muchly for the redirect to the FAQ.
1) I'd like to see a C.2 rev where the entire system is put on a 16 bit ISA card, for use in a passive backplain.
2) for clock generation, have a look at the Silicon Labs Si5351 series of chips, they are I2C controlled PLL chips that output 3 to 8 independently configurable outputs between 3Khz to 290Mhz.