Commander X16

To me, the X16 is like a TG16 with better graphics and sound. I think of it like 4th gen / 16bit era. Sure, the CPU’s 8bit but so was the TG16….

On 12/27/2021 at 8:48 PM, Edmond D said:

... Finally, any product has a target market with a price to hit that crowd. The general consumer market always likes a low price. I remember the early 80's 8 bit marketing was either price, the number of colours or the RAM size. Companies may have wanted my geeky teenage self to go buy something, but it was normally cost prohibitive to me. ?

Yes, it was a windfall as a dependent of a veteran that enabled me to buy my C64 / 1541 / monochrome monitor system in 1981. I was expecting to have the best computer in my dorm when I got back to University, but there was a kid from a better heeled family who had a IBM-PC with dual disk drives and 128KB RAM!

For quite a while, more expensive systems were things I read about in Byte Magazine, not things I was in the market for. I eventually scraped up enough to buy a daisywheel printer, but most of my games and programs were typed in from computer magazines rather than store bought. I had a truly atrocious assembler written in Basic, and the quirky but quite useful Busy Bee Perfect Writer as a word processor.

I got a C128D plus external 1581 and 1571 with some of my Peace Corps readjustment allowance from teaching Math in Grenada in the West Indies, then fried it all to quickly after arrival by plugging the printer power tap into the datasette port upside down, frying the 8502, leaving me with a C64 with 1571 and 1581 drive, and daisywheel printer, that I ended up taking to grad school.

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I think the Turbo-Grafx16 comparison is not all that far off ... it is based on a 65C02 processor (though with added bits) that can run at either 1.79MHz or 7.16MHz, and the TurboGrafx video chipsets used a 16bit datapath to have more processing bandwidth than a VIC-II generation graphical chip could handle. As 16bits at 7.16MHz is about 1/3 the bandwidth of 8bits at 50MHz, one would hope that Vera would outperform it. And while a PSG was built into the TG16's CPU with four channels of wavetable playback, a basic FM synthesis option from combining the first two of the channels, and a kind of PCM playback, the X16 Audio is also more capable.

If the HuC6280 was still in production, they might have used that and CPU with 64KB logical address space, 2MB physical address space and PSG would have been locked in from the start ... but it's not, so it wasn't an option.

On 12/26/2021 at 10:47 PM, BruceMcF said:

The VIC-II and the MOS 8563 were both pretty much "black boxes" where things happen. Understanding down to the level of what register to set to get what effect in the VIC-II, MOS 8563 or Vera seems to be similar levels. Obviously if Dave owned his own fab, and if the X16 was expected to sell in the millions, Vera could be done as a +5v compatible ASIC chip.



The whole system based on parts which were available in the 80s was not part of the vision of the project ... that would be a different project. That's not to say that other project is unworthy or anything, but "build to the extent possible with DIP ASIC parts currently in production" and "build with parts which were available in the 80s" are two different goals that are going to disagree substantially.



Indeed, the alternative "chips available in the 80s" goal is violated quite extensively by the X16. Byte addressed 512KB Static RAM chips were not readily available in the 80s, and that's a big part of the chip count of the "big" chips in the system. Nor were 14MHz rated 65C02 or 6522 chips.

 

On 12/27/2021 at 9:36 AM, Wavicle said:

A component with the capabilities of VERA in the 80's would have been prohibitively difficult to bring to market. The tooling to create a die large enough to hold 1Mbit of SRAM just didn't exist at the time. It's difficult to appreciate how many Moore's-Law-Doubling-Transistor-Count-Cheaply cycles we've gone through since then. Had Commodore sunk every dime of profit they ever made into the custom tooling necessary to produce such a component at the node size achievable at the time, they would still have been hundreds of millions of dollars short of what was needed.



A 1989 VERA would have to have been its own board. Even then it would have been very difficult and prohibitively expensive. 8-bit systems were all about not being prohibitively expensive.

 

On 12/27/2021 at 10:59 PM, Wavicle said:

Moving the video RAM off-chip presents a packaging problem. 32 VRAM data pins + 15 VRAM address pins + 17 system interface pins (8 data, 5 address, CS, RWB, clock, INTB) + video clock + 5 pins video out (analog RGB, Hsync, Vsync) + 2 power pins puts the lower limit of pin count at 72. Even more to support audio and a mass storage interface (and a few others like the VRAM RWB pin and whatever else I can't think of off the top of my head). There may have been 80 pin DIP packages, but the largest I am aware of is the 64 pin MC68000. VERA would have been too large for a through-hole DIP package and would have been a surface mount component. At some point we have to admit that it would look sorely out of place among all other 8 bit components on the PCB. VERA's capabilities are defined more by what the FPGA it is using today can do than what would have been a practical graphics solution in the age of 8 bit systems.

so i may have maybe not used the right term here.

what i tried more to say, is, that i think the goal was to build a computer with 5V ASIC chips, not depending if they were avaiable in the 80s.



but still i do beleve, that if commodore made his in the 80s, they would at least have had the Vram seperately and some other capabilities wich the Vera chip now has would have been seperately.

i am not like wanting to have a graphics unit wich makes every function with its own chip. but i would like to at least probe around in th Vram or adjust timing sgnals to mess with screens and stuff like this, wich is not possible in th Vera chip, would be easely  possible in for example in a C64

On 12/27/2021 at 10:59 PM, Wavicle said:

Moving the video RAM off-chip presents a packaging problem. 32 VRAM data pins + 15 VRAM address pins + 17 system interface pins (8 data, 5 address, CS, RWB, clock, INTB) + video clock + 5 pins video out (analog RGB, Hsync, Vsync) + 2 power pins puts the lower limit of pin count at 72. Even more to support audio and a mass storage interface (and a few others like the VRAM RWB pin and whatever else I can't think of off the top of my head). There may have been 80 pin DIP packages, but the largest I am aware of is the 64 pin MC68000. VERA would have been too large for a through-hole DIP package and would have been a surface mount component. At some point we have to admit that it would look sorely out of place among all other 8 bit components on the PCB. VERA's capabilities are defined more by what the FPGA it is using today can do than what would have been a practical graphics solution in the age of 8 bit systems.

im gonna leak a bit here, because the developement of my proect is technicly still unnanounced and secretive.



but i and a couple of friends of mine are right now developing on a CX16 Graphics solution with only ASIC chips.

the main idea is to use CPU driven graphics. A circuit witch displays the content of a deticated Vram out onto a VGA port (ben eather made a excelent Video about that) and with a bit of enhancing you can use that circuit fairly well.



then we are planning on using a Motorola 68K CPU because it has a 24bit adressbus, wich means support to up to 16Mbyte ram, witch we gonna use almost nothing of it, because 256Kbytes are enough for the simple prototype first.

(ideas of supporting higher resolutions and so on more ram are existing, we just dont want to bite more than we can chew.)

this CPU should then make all the Tilelogic, sprites and look up of two character sets, one is hardcoded in rom, and the other one is loadeable...



as i said, it is still in early developement, but i have high hopes that it may work fairly well.

(I do not expect or even hope that it gets added to the CX16 stock, but maybe it will be a fun addon card)

 

On 12/27/2021 at 2:59 PM, Wavicle said:

Moving the video RAM off-chip presents a packaging problem. 32 VRAM data pins + 15 VRAM address pins + 17 system interface pins (8 data, 5 address, CS, RWB, clock, INTB) + video clock + 5 pins video out (analog RGB, Hsync, Vsync) + 2 power pins puts the lower limit of pin count at 72. Even more to support audio and a mass storage interface (and a few others like the VRAM RWB pin and whatever else I can't think of off the top of my head). There may have been 80 pin DIP packages, but the largest I am aware of is the 64 pin MC68000. VERA would have been too large for a through-hole DIP package and would have been a surface mount component. At some point we have to admit that it would look sorely out of place among all other 8 bit components on the PCB. VERA's capabilities are defined more by what the FPGA it is using today can do than what would have been a practical graphics solution in the age of 8 bit systems.

Like on the X16, VERA would have been a daughter board, in much the same way Soundblaster was. Those edge connectors can have lots of pins.

I just watched a talk that Bil Herd gave about his time at Commodore. What was the thing he fought for on the C128? A reset circuit. And he's part of this group. If that attiny reset circuit is giving the devs headaches, maybe bring in the reset circuit ringer?

On 12/29/2021 at 6:28 PM, Ed Minchau said:

Like on the X16, VERA would have been a daughter board, in much the same way Soundblaster was. Those edge connectors can have lots of pins.

Great idea. I really like that one!

Was it also not the plan from the beginning IIRC?

On 12/29/2021 at 8:47 AM, Mutz03 Zockt said:

... so i may have maybe not used the right term here.

what i tried more to say, is, that i think the goal was to build a computer with 5V ASIC chips, not depending if they were avaiable in the 80s.



but still i do beleve, that if commodore made his in the 80s, they would at least have had the Vram seperately and some other capabilities wich the Vera chip now has would have been seperately. ...

In the 80s, sure, it would have been separate VRAM just like the MOS 8563 in the C128, for exactly the same reasons. An integrated RAM component would have been prohibitively expensive. It would have been DRAM, for cost reasons.

Today, the integrated RAM comes with the commodity priced FPGA part, so that's the cheaper approach.

Whether it would have all been that integrated ... I guess it depends on whether it was TED philosophy Commodore or Commodore 128 philosophy Commodore.

On 12/29/2021 at 5:55 AM, Mutz03 Zockt said:

as i said, it is still in early developement, but i have high hopes that it may work fairly well.

It sounds like an intriguing project - I hope it goes well for you and your team.

On 12/29/2021 at 5:55 AM, Mutz03 Zockt said:

im gonna leak a bit here, because the developement of my proect is technicly still unnanounced and secretive.



but i and a couple of friends of mine are right now developing on a CX16 Graphics solution with only ASIC chips.

the main idea is to use CPU driven graphics. A circuit witch displays the content of a deticated Vram out onto a VGA port (ben eather made a excelent Video about that) and with a bit of enhancing you can use that circuit fairly well.



then we are planning on using a Motorola 68K CPU because it has a 24bit adressbus, wich means support to up to 16Mbyte ram, witch we gonna use almost nothing of it, because 256Kbytes are enough for the simple prototype first.

(ideas of supporting higher resolutions and so on more ram are existing, we just dont want to bite more than we can chew.)

this CPU should then make all the Tilelogic, sprites and look up of two character sets, one is hardcoded in rom, and the other one is loadeable...



as i said, it is still in early developement, but i have high hopes that it may work fairly well.

(I do not expect or even hope that it gets added to the CX16 stock, but maybe it will be a fun addon card)

 

I think that's going to require much more than a bit of enhancing. I don't want to discourage you, but I would encourage you to focus on crawling before flying. How will communication between your card's CPU and 6502 take place? The 6502 bus has strict timing constraints that are extremely difficult to meet via software implementation on a microcontroller. It's pretty much impossible to handle 6502 bus IO using interrupts on the 68K because that CPU has a 44 clock cycle minimum latency to service interrupts. An 8MHz 6502 bus read has an allowance of about 50ns from the rising edge of PHI2 until the data needs to be stable on the data bus to meet the data setup time constraint (tDSR in the datasheet, I think). If you're using all discrete logic, the fastest discrete 7400 series logic chips have a propagation delay of 4-8ns under ideal circumstances. The problem could probably be solved if you're sufficiently clever, but it would be quite the labor of love compared to just sticking a low cost FPGA in there for interfacing with the 6502 bus.