Commander X16

Just a correction, I meant writing DMA contoller registers in the $9F60-$9FFF range.

Gotcha. Yes. As for how to go about assigning a specific address range, I'm sure that could be done easily enough in Verilog, but it would probably be ideal to rely on external logic to select the DMA controller for the appropriate range of addresses and assert a pin. A problem for someone else, or for me whenever I would get around to testing it. Which is why, way back on the first post, I was thinking it would need a "chip enable" pin, or equivalent, to indicate when it's been selected.

It seems like the alternative that makes the address range configurable would be to rely on more pins that are permanently tied high or low (either with traces or DIP switches), to select the appropriate address range the controller should respond to.

StephenHorn wrote: ↑Wed Mar 08, 2023 9:20 pm My plan, at least, was not to add DMA to the VERA itself -- the VERA is well too complicated for my nascent understanding of Verilog. And if RDY doesn't allow another device to use the bus (such as the CPU leaving its address/data lines set based on whatever it was last doing), then my plan is toast anyways.

I think Dacobi has the concept; when you write to the VERA address range, VERA handles it.

As to RDY: pulling RDY before the falling edge of Phi2 puts the CPU into a high-impedance state. This means that the CPU is effectively disconnected from the bus until RDY is de-asserted.

There's also another trick which may be helpful: In order to allow display hardware to operate alongside the 6502, the CPU only uses half of the bus cycle. You may be able to do half-cycle DMA by working in the second half of the bus cycle.

https://retrocomputing.stackexchange.co ... 502-system

(this shortened bus cycle is why the 6502 can do things in one bus cycle that takes 2-4 on another CPU. The 6502 isn't faster or more efficient; it just has a different relationship to the clock than an 808x chip.)

** correct "low" to "high" impedance.

It seems like the alternative that makes the address range configurable would be to rely on more pins that are permanently tied high or low (either with traces or DIP switches), to select the appropriate address range the controller should respond to.

How does it work with the cartridge design and different expansion slots?

Just so I understand. The board will assert a IO3-7 Select line depending on which IO range is being written to. So you're taking about a way to tell Verilog which slot the module is occupying?

Dacobi wrote: ↑Wed Mar 08, 2023 11:50 pm How does it work with the cartridge design and different expansion slots?

Just so I understand. The board will assert a IO3-7 Select line depending on which IO range is being written to. So you're taking about a way to tell Verilog which slot the module is occupying?

It doesn't matter which slot you're using; all 4 slots have access to IO3-IO7, which is why you need DIP switches or jumpers. Cards can't be allowed to just pick an I/O range, or we will end up with conflicts where two different cards pick the same I/O block.

This has nothing to do with Verilog. This is just a hardware switch. In the case of a DIP switch, you have five on/off switches with IO3-IO7 connected to the input side of the switch. The outputs are all tied together and go to the Chip Select for the chip(s) on the card.

As to the cartridge design: the cartridge is just an expansion card in a pretty case. There's no difference (so far) between a Gen-2 cartridge and a Gen-1 expansion card, other than the size of the board.

This has nothing to do with Verilog. This is just a hardware switch. In the case of a DIP switch, you have five on/off switches with IO3-IO7 connected to the input side of the switch. The outputs are all tied together and go to the Chip Select for the chip(s) on the card.

The way I understand it Chip select would only be asserted when the DIP switches are set to match the correct IO select line?
What I meant was that the DIP switches could then tell the FPGA which IO range to use?
(Edit) If you had 4 traces going to 4 different pins on the FPGA, beside the combined outputs going to Chip select.
By the way, why are there 5 IO select lines but only 4 expansion slots?

From what I've seen of the cartridge design it doesn't have any DIP switches?

Dacobi wrote: ↑Thu Mar 09, 2023 9:45 am

This has nothing to do with Verilog. This is just a hardware switch. In the case of a DIP switch, you have five on/off switches with IO3-IO7 connected to the input side of the switch. The outputs are all tied together and go to the Chip Select for the chip(s) on the card.

The way I understand it Chip select would only be asserted when the DIP switches are set to match the correct IO select line?
What I meant was that the DIP switches could then tell the FPGA which IO range to use?
(Edit) If you had 4 traces going to 4 different pins on the FPGA, beside the combined outputs going to Chip select.
By the way, why are there 5 IO select lines but only 4 expansion slots?

From what I've seen of the cartridge design it doesn't have any DIP switches?

I don't know why there is an extra IO select line. It's possible the answer is "because there was a memory range leftover, so why not?"

Tom's cartridge doesn't have any DIP switches because it doesn't have any devices that want to live in the $9F60-$9FFF range. His cartridge design right now is just memory chips. Version 1 was just more of the same kinds of parallel I/O chips used to populate the board's memory, they're mapped to the ROM address range ($C000-$FFFF) for ROM banks $20-$FF, and the cartridge knows the current ROM bank thanks to the ROMB0-ROMB7 lines on the expansion slot. The "version 2" cartridge includes some serial I/O memory that is accessed through the I2C interface (the SDA and SCL pins of the expansion slot).

I think I get the general concept except one last question regarding PHI2.
Do you read on one clock pulse and write on the next or is it something with pos/neg edge?

On a side note, I should probably find a course on address logic and memory layouts etc : )

Dacobi wrote: ↑Thu Mar 09, 2023 9:45 am The way I understand it Chip select would only be asserted when the DIP switches are set to match the correct IO select line?
What I meant was that the DIP switches could then tell the FPGA which IO range to use?
(Edit) If you had 4 traces going to 4 different pins on the FPGA, beside the combined outputs going to Chip select.

The FPGA doesn't know or care about the full 16-bit address. Remember how binary addressing works; the card only decodes the lower 5 bites on the address bus. The upper 11 bits don't matter, because IO3-IO7 guarantees that the address is already in a specific range.

So passing all IO lines into the FPGA is a poor design, since it's wasted space and resources. instead, you just route one IO line in. The DIP switch or jumper header simply chooses which of those 5 IO lines gets routed in.

By the way, why are there 5 IO select lines but only 4 expansion slots?

Because there were 5 I/O blocks free. I/O block ranges are limited to powers of 2, and VERA only had 5 address lines, so it was a simple choice to make the standard I/O block 32 bytes wide.

Note that it is possible for a card to use 2 I/O blocks. Consider a combo card with a serial port and a MIDI controller. You might choose to map both UARTs to their own address space, so you'd have two jumper blocks, one for each UART.

The FPGA doesn't know or care about the full 16-bit address. Remember how binary addressing works; the card only decodes the lower 5 bites on the address bus. The upper 11 bits don't matter, because IO3-IO7 guarantees that the address is already in a specific range.

That makes sense, but then I don't understand what StephenHorn meant by this?

As for how to go about assigning a specific address range, I'm sure that could be done easily enough in Verilog, but it would probably be ideal to rely on external logic to select the DMA controller for the appropriate range of addresses and assert a pin. A problem for someone else, or for me whenever I would get around to testing it. Which is why, way back on the first post, I was thinking it would need a "chip enable" pin, or equivalent, to indicate when it's been selected.

It seems like the alternative that makes the address range configurable would be to rely on more pins that are permanently tied high or low (either with traces or DIP switches), to select the appropriate address range the controller should respond to.