Commander X16

Posted: **Thu Jun 29, 2023 4:37 pm**

spargue wrote: ↑Thu Jun 29, 2023 3:34 pm
That's not the function of the RDY pin. You should read the posts further back as to why the card is reading $0001.
The issue is the sequence of operations to enter / exit an interrupt / bank switch and whether the card can do so whenever or if it needs a specific preamble sequence to allow mastering. If the ISR is relying on the RAM $0001 to be a shadow of the latch state is there a specific hazard where a card can jump in and mess with it thus violating the shadow state? the ISR is assuming the latch is still $00 and the RAM $0001 is the old value; but if a bus master occurs during this sequence that does its own bank sequence, then the latch is no longer $00 but the old value.

That is a perfectly valid function of the RDY pin. A bidirectional pin for use by DMA controllers is fair to use as a bidirectional pin by DMA controllers. This isn't a controversial position.

I think there may be a flaw in your reasoning and you are missing something critical. Looking at the IRQ's first few instructions:

Code: Select all

__irq:
	pha
	lda rom_bank    ;save ROM bank
	pha
	stz rom_bank	;set KERNAL bank

These are the only instructions executed where the ROMBANK register and the shadow copy are out of sync. This IRQ handler code lives in RAM. Where does the card initiate bus mastering and cause an issue? It is fairly trivial for a card reading $01 to detect that it is dangerous to start bus mastering at this time.

Posted: **Thu Jun 29, 2023 6:24 pm**

spargue wrote:the ISR is assuming the latch is still $00 and the RAM $0001 is the old value; but if a bus master occurs during this sequence that does its own bank sequence, then the latch is no longer $00 but the old value.

The ISR assumes but does not depend on RAM $0001 and the latch being out of sync with each other.

A card is under no obligation to restore that specific inconsistent state.

It's OK to return control to the CPU with $0001 and the latch in sync with each other, even during the part of the ISR that assumes they may be out of sync. At no point does this cause issues.

Commander X16

Access to banked memory by expansion cards

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Re: Access to banked memory by expansion cards