Re: User Port Dreams: SPI
Posted: Fri Oct 13, 2023 7:19 pm
We are now in the "J4" era, with the J4 block pin header containing the extra VIA#1 pins:
Pin1: CA1
Pin2: CA2
Pin3: PB0
Pin4: PB1
Pin5: PB2
Pin6: CB2
I note that one option for use of an SPI bus is a serial UART, where the MAX3100 is a simple UART with 8 byte buffers. There are also SPI accessed USB and WiFi bridges. And the J4 block pin header can easily support an SPI bus with two selects and one common /alert:
SPI_SCLK := Pin3, PB0, since this allows INC PORTB and DEC PORTB to toggle the clock)
SPI_MISO =: Pin4, PB1, this allows "LDA PORTB : ROR : ROR" to extract the input bit
SPI_MOSI := Pin5, PB3, since this can be written with "LDA #MOSI : TSB PORTB" or "LDA #MOSI : TRB PORT B".
CA2 is the device selects, since the handshake control register allows it to be set to 0 or 1.
CA1 is the /Alert line, if you should have an SPI servant device that pulls a line low to signal to the bus master that it needs attention/
It can also be easily set up to support the seven device hobbyist SPIB interface, since a Universal serial shift register (74x299) can be set up so that one line puts it in shift mode when high and hold mode when low, and the same line can be tied to an Output Enable to also assert the contents of the register when pulled low. With a network resister to provide pull up resisters on the outputs, when setting the select register for writing a new select state, all devices are automatically de-selected.
If the SPI bus is accessing a device on the same internal daughter-board, perhaps a tap that plugs int the edge of a slot can provide +5v, GND -- also +3.3v and/or +/- 12v if desired. If it clips to the side of the slot, then it cannot be placed incorrectly, because turning it around and plugging it into the other end of the slot gives the same power and ground locations.
Pin1: CA1
Pin2: CA2
Pin3: PB0
Pin4: PB1
Pin5: PB2
Pin6: CB2
I note that one option for use of an SPI bus is a serial UART, where the MAX3100 is a simple UART with 8 byte buffers. There are also SPI accessed USB and WiFi bridges. And the J4 block pin header can easily support an SPI bus with two selects and one common /alert:
SPI_SCLK := Pin3, PB0, since this allows INC PORTB and DEC PORTB to toggle the clock)
SPI_MISO =: Pin4, PB1, this allows "LDA PORTB : ROR : ROR" to extract the input bit
SPI_MOSI := Pin5, PB3, since this can be written with "LDA #MOSI : TSB PORTB" or "LDA #MOSI : TRB PORT B".
CA2 is the device selects, since the handshake control register allows it to be set to 0 or 1.
CA1 is the /Alert line, if you should have an SPI servant device that pulls a line low to signal to the bus master that it needs attention/
It can also be easily set up to support the seven device hobbyist SPIB interface, since a Universal serial shift register (74x299) can be set up so that one line puts it in shift mode when high and hold mode when low, and the same line can be tied to an Output Enable to also assert the contents of the register when pulled low. With a network resister to provide pull up resisters on the outputs, when setting the select register for writing a new select state, all devices are automatically de-selected.
If the SPI bus is accessing a device on the same internal daughter-board, perhaps a tap that plugs int the edge of a slot can provide +5v, GND -- also +3.3v and/or +/- 12v if desired. If it clips to the side of the slot, then it cannot be placed incorrectly, because turning it around and plugging it into the other end of the slot gives the same power and ground locations.