Sorry for committing thread necromancy, but i have a question, would a dedicated DSP chip (because those still exist for some reason) be cheaper than an FPGA large enough to hold an OPM emulation?
If so, I wonder if you could program a DSP chip so it can do "frequency" (read: phase) modulation, then paper over the differences for compat. with old software with some glue logic - ideally in the VERA FPGA, but if simple enough small external GAL would work as well.
Will YMF825 (SD-1) be the ultimate answer to YM2151 (and maybe ymf262)shortage?
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The SD-1 is dead... but DSP chips are not dead yet?
everything is so broken building anything is like building on a pile of sand -me 5 dec. 2023
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VERA suggs: Extra PSG Waves(viewtopic.php?t=6923) Togg Opacity and Bitmap Fine Addr.(viewtopic.php?t=6981)
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Re: SD-1 [...] More thinking about what would be required.
After some thinking... yea no. To keep up with a single OPL3 will require calculating an operator in 8 cycles or less - good luck doing that with a DSP that isn't more expensive than an FPGA solution... unless you can get the DSP running at 6x input clock speed?
After all, most DSPs, even cheap ones (such as a Microchips dsPIC33 or a Texas Instruments TMS320C55x-series), seem to be able to run at 100MHz, with an input clock of 14.32MHz you'd almost be capable of doing a 7x overclock... to be safe let's go with 6x, which means running at about 86MHz, and calculating an operator in 48 cycles or less, something that seems almost doable.
A DSP like that costs around 5-10 USD, at that price you can get an FPGA with around 1280 LUTs (such as a Lattice ICE40 (LP|HX)1K), which can, I suspect, be run at around 30-50MHz when bearing an FM synthesis configuration.
I'm unsure as to which would be better... especially since imho if these can make a better-than-OPL3 simulation, they probably should, so "good enough" really isn't...
After all, most DSPs, even cheap ones (such as a Microchips dsPIC33 or a Texas Instruments TMS320C55x-series), seem to be able to run at 100MHz, with an input clock of 14.32MHz you'd almost be capable of doing a 7x overclock... to be safe let's go with 6x, which means running at about 86MHz, and calculating an operator in 48 cycles or less, something that seems almost doable.
A DSP like that costs around 5-10 USD, at that price you can get an FPGA with around 1280 LUTs (such as a Lattice ICE40 (LP|HX)1K), which can, I suspect, be run at around 30-50MHz when bearing an FM synthesis configuration.
I'm unsure as to which would be better... especially since imho if these can make a better-than-OPL3 simulation, they probably should, so "good enough" really isn't...
everything is so broken building anything is like building on a pile of sand -me 5 dec. 2023
VERA suggs: Extra PSG Waves(viewtopic.php?t=6923) Togg Opacity and Bitmap Fine Addr.(viewtopic.php?t=6981)
VERA suggs: Extra PSG Waves(viewtopic.php?t=6923) Togg Opacity and Bitmap Fine Addr.(viewtopic.php?t=6981)