Commander X16

Originally, there were (I believe) up to 32 banks of ROM.  I.E. only 128K of ROM planned, so only need 5 bits to select the one you want.

But, I think that's been tweaked to allow theoretically 256 banks.

That suggests a potential upper limit of 4MB of ROM.

Is that correct?

The current specification part of the FAQ for the ROM says the "TBD" is 128 banks of ROM or RAM, so, if it goes the ROM side of that, it would be a 2M flash ROM.

Without contention for the VIA GPIO lines anymore, it seems like the "magic latch" approach would indeed allow for 4M, but IIRC it's 2M one of the team members mentioned as the target.

That sounds cool, but how would it be tweaked?

Some surprise RAM there would be pretty nice! A page size of 16kb would also be a nice chunk though even if we don't get that, having some ROM space to store common libraries and things like trig lookups tables, etc. is something I'm excited about and how we see some standard materialize to use that space.

But of course - well, if I could have _one_ feature, it would be hardware ADSR envelopes for VeraSound ? But if I could have TWO, having some extra 16kb RAM pages would be pretty cool!

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if I could have _one_ feature, it would be hardware ADSR envelopes for VeraSound

I cannot agree more.

But, Vera is already finalized.

 

2 hours ago, m00dawg said:

if I could have _one_ feature, it would be hardware ADSR envelopes for VeraSound

While it would be nice to have ADSR envelopes on the VERA PSG, the lack of envelopes on the PSG does help balance the X16's otherwise extremely powerful audio capabilities.

7 hours ago, xanthrou said:

That sounds cool, but how would it be tweaked?

No tweaking required for the ROM side of the "TBD", once they switched to a dedicated latch addressed at $0001, there is no obstacle to connecting as 7 or 8 outputs to the ROM high address lines rather than 5 ... 512K ROM was more about contention for various uses of the VIA GPIO pins, and so when ROM bank select was taken away from the VIA, that contention went away.

The difference between 512KB and 2MB is connecting two more outputs of an octal latch and bumping up that part of the parts bill. 2M as an upper end might be what is available in production in a through hole form factor, or a cost/benefit trade-off.

The "or RAM" is too vague to read a lot into it. It could refer to access to the existing HighRAM, it could refer to different possibilities in different phases ... and since it is a TBD, if the decision ends up going against, we'd likely not know what it refers to anyway.

But one (very) hypothetical possibility is that a way to get the effect of "programmable ROM" rather than allowing the FlashROM to be ISP is to have ROM banks with the high bit set accessing HighRAM in read only mode. That would reduce risk of people bricking their system (which ALWAYS happens when firmware is ISP In a consumer product ... you can find multiple versions of "what to do if you bricked your device" for all of the popular handheld Chinese game consoles) ... and reduce the bill of materials for the FlashROM ... but increase the cost and complexity of the addressing logic. The latter is why I would be skeptical whether it IS the "TBD", and if it is, whether it would end up landing "Yes".

But anyway, then $00-$7F would just mirror the 512KB FlashROM four times, since only b0-b4 would be hooked up to FlashROM address lines, and the user would decide how much of the HighRAM they want to allocate to "high ROM" bank usage for $81 through $FF (given that HighRAM banks 0 and 1 are already spoken for).

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2 hours ago, Elektron72 said:

While it would be nice to have ADSR envelopes on the VERA PSG, the lack of envelopes on the PSG does help balance the X16's otherwise extremely powerful audio capabilities.

It also is a factor helping to push retention of the YM2151, which if it is included will help lock down a very 80s sound to some of the audio output of the CX16.