Commander X16

Seeing the technical depth of discussions from several engineers here has made me wonder.  

Many of you have 65C02s handy.  Some have Ben Eater's kits.  I watched his videos.  And I've recently looked at SRAMs on Mouser.

And you guys know all about this stuff.  I mean some of you actually understand ALL of what's going on.

Just by using Ben's videos, I could probably get a 65C02 connected to the KERNAL (on EEPROM) and a static RAM.  Assume a non-banked memory model.

I mean, the design is COTS on purpose.  If I can get that far, some of you could get quite a bit farther.  VERA notwithstanding.

Am I right?

 

I may not have a VERA, but I do have some YM2151 chips ?

Seriously, though, I suspect this is a great big honkin' example of ye olde "Dunning-Kreuger" in action for most of us. Sure, we know how clock cycles work, how busses work, how to hook up all this stuff and how it talks to each other, but the complexity goes much deeper than an Eater student (myself included) must realize.

The 8MHz barrier has proven quite the hurdle for the team. I know Kevin has quite a bit of experience making real circuits / boards / etc. If the likes of him and M. Steil have trouble getting the real HW to make liftoff, then clearly someone like me who understands quite a bit of the theory of what's going on would face many unforeseen obstacles and challenges. I'm sure an O-scope is pretty much mandatory to live in that realm, and I have none. I think Adrian's video where he talks about his assistance in troubleshooting proto 2 is an eye-opener to just how sensitive these timing issues really are. And then there's capacitance issues with the traces, etc - none of which we know much about from breadboarding videos except the basic introduction to the topic when Ben demonstrated how harmonics of the clock signal will be attenuated as the clock speed increases.

 

1 hour ago, ZeroByte said:

Seriously, though, I suspect this is a great big honkin' example of ye olde "Dunning-Kreuger" in action for most of us. Sure, we know how clock cycles work, how busses work, how to hook up all this stuff and how it talks to each other, but the complexity goes much deeper than an Eater student (myself included) must realize.



[...snipped Adrian's Digital Basement mention re timing...]

Granted.  I mean, I get that.  The X16's problems are Adrian Difficult.

So, what about backing it to Amateur Difficult?  Can I build a Neanderthal X16?

 

I'll write before I think: how about the Ben Eater design (or for that matter the W65C02SXB) with the MIST KERNAL?

The short answer is: no.  The KERNAL really depends on hardware being a certain way.  I suspect it won't work at all with bits missing.  The whole POINT of much of MIST's KERNAL is that it makes use of all the special hardware in the X16, that is, VERA, and the banks.

 

The longer answer is: this is what 8BG went through already.  A KERNAL would have to be written, and almost none of it could be ported from the existing KERNAL. 

Even Ben himself struggled with (or pretends to in order to make vids more dramatic w tasty teaching moments) timing diagrams and issues.

Quadrupling the clock speed doesn’t lend to improved tolerance.  Before architectures drastically changed in the 90s, wait states were necessary and while I’m no expert, it’s clear that some of this isn’t as simple as it looks on TV.

Whomever is left should throw in the towel and just release a 2mhz version so people can get their grubby hands on something.

OR slow down to snails pace during SD card IO and revert to a non PS/2 kbd.  Wouldn’t be the first.  Or off-board it to a C=key.  I think the Vera working right (sounds like they already have this?) is the important part.

In summary, take my f’ing money already,‘good enough is good enough’.

We already lost that cry baby guy that left a month or two ago after making a stink in the retro forum, and now Christian has jumped.

 

4 hours ago, ZeroByte said:

 And then there's capacitance issues with the traces, etc - none of which we know much about from breadboarding videos except the basic introduction to the topic when Ben demonstrated how harmonics of the clock signal will be attenuated as the clock speed increases.



 

I believe this is a four layer board. The Vcc plane and Ground plane in the middle do a lot to mitigate those capacitance issues. Not all of course. 

8 hours ago, ZeroByte said:

The 8MHz barrier has proven quite the hurdle for the team.

Yes, I also noted that to myself. And I remeber Ben Eater said in one of the videos something like, that his projects work well on breadboards because of low speeds (like 1 MHz). So I think what @rje is proposing might be possibe at slow speeds only.

10 hours ago, rje said:

Seeing the technical depth of discussions from several engineers here has made me wonder.  



Many of you have 65C02s handy.  Some have Ben Eater's kits.  I watched his videos.  And I've recently looked at SRAMs on Mouser.



And you guys know all about this stuff.  I mean some of you actually understand ALL of what's going on.



Just by using Ben's videos, I could probably get a 65C02 connected to the KERNAL (on EEPROM) and a static RAM.  Assume a non-banked memory model.



I mean, the design is COTS on purpose.  If I can get that far, some of you could get quite a bit farther.  VERA notwithstanding.



Am I right?



 

I've been thinking of buying the WDC W65C02SXB  development board and adding some RAM to that. That makes more sense to me than building a system from scratch. It would require a text terminal for display, but I actually have one of those in a project box right now.

I believe there's also a RC2014 6502 board out there. In fact, here's an example: http://forum.6502.org/viewtopic.php?f=4&t=4571

That has the advantage of being a proven design with support already out there in the wild. 

10 minutes ago, TomXP411 said:

I've been thinking of buying the WDC W65C02SXB  development board and adding some RAM to that. That makes more sense to me than building a system from scratch. It would require a text terminal for display, but I actually have one of those in a project box right now.

I've been thinking about borrowing pieces from MiSTer cores to build a custom machine based on 65816 with a full address space. I don't think in a physical circuit mindset (yet), but think it would be cool to instantiate something that has a certain cadre of HDL based chips. It could then be fun to extend the 65816 using the "reserved for future use" opcode.

1 hour ago, Scott Robison said:

I've been thinking about borrowing pieces from MiSTer cores to build a custom machine based on 65816 with a full address space. I don't think in a physical circuit mindset (yet), but think it would be cool to instantiate something that has a certain cadre of HDL based chips. It could then be fun to extend the 65816 using the "reserved for future use" opcode.

That sounds interesting. In my 65816 emulator, I used the WDM opcode for things that a physical machine would never do: throttling back the emulator, to let the host CPU slow down, for example. That would also be a good place to stick MUL and DIV instructions... maybe with signed and unsigned variants. 

 

 

11 hours ago, rje said:

Granted.  I mean, I get that.  The X16's problems are Adrian Difficult.



So, what about backing it to Amateur Difficult?  Can I build a Neanderthal X16? ...

As in, 6.25 MHz? I/O page at $C000-$C0FF overlaying the bottom page of the 16K ROM window, a single 512K RAM and a 64K RAM with the bottom 32K of Low RAM locked at $0000-$7FFFF, an 8K window at $8000-$9FFF and another at $A000-$BFFF, the high window six bits of banks over the full range of 512K, the low window two bits of four 8K banks for the other 32K of Low RAM?