Could the User Port be set up to better support EPP (Enhanced Parallel Port)?

[BruceMcF]

In the FB group is a block header pinout for a parallel port.

Translating to the standards documents pinouts for parallel ports, which are (block header# ->parallel port pin#):

1->1, 3->2, 5->3. 7->4, 9->5, 11->6, 13->7, 15->8, 17->9, 19->10, 21->11, 23->12, 25->13

2->14, 4->15, 6->16, 8->17, 10->18, 12->19, 14->20, 16->21, 18->22,  20->23, 22->24, 24->25, 26->NC

The block header pinout shows parallel port pin #1 at PB0, pin#12-#15 at PB1-4, pin#16 (block header 6) is shown as an inverted line connected to RESB, the VIA6522 reset line. So when RESB is High, the Initialize signal is Low.

In the EPP protocol, this seems to mean that in order to use the external device Reset output (in EPP mode), you must also reset the VIA6522. It would be more convenient if the EPP external device initialize line was on a GPIO.



The EPP doesn't use as many input lines as the Standard Parallel Port, because it relies on setting the correct IDE register address(es) and then reading the register(s) contents in order to determine what is the reason for the external device raising an Interrupt. Therefore parallel port pins 12 &13 (Block header 23 & 25) connecting to PB1&2, and parallel port 15 (Block Header 4) connecting to PB4 are Spare pins in the EPP protocol. https://allpinouts.org/pinouts/connectors/parallel/epp-parallel/



So a jumper that selects between the spare PB4 to go out on the block header pin 6 (parallel port pin #16) rather than the inverted mirror of the RESB being sent to the VIA would seem to suffice to allow an external EPP device to be reset without also having to reset the 6522.



 

[TomXP411]

Is this the diagram you were looking at? 

 



 

It looks  to me like there are 14 GPIO lines (PA0--7 and PB0-5). I'm not sure what the CA lines are... are those connected to the bit shifters on the VIAs?

So if I'm reading that right, we should be able to use PA0-7 for bidirectional parallel data lines and PB0-5 for clock, CS, and flow control lines. 

 

[BruceMcF]

6 hours ago, TomXP411 said:

It looks  to me like there are 14 GPIO lines (PA0--7 and PB0-5). I'm not sure what the CA lines are... are those connected to the bit shifters on the VIAs?



So if I'm reading that right, we should be able to use PA0-7 for bidirectional parallel data lines and PB0-5 for clock, CS, and flow control lines.

I am referring to the existing EPP protocol ... the one, for example, which I used to use in my PC compatible luggable to connect to my external hard drive.

CA1 and CA2 are the Port A handshake lines. Looking at the VIA datasheet, CA1 can indeed be used to store an alert in a VIA register which can either be polled or can generate an IRQ. It can be set for either negative or positive edge, so no conflict with the EPP protocol there: set it to detect a negative edge.

CA2 has four input modes and four output modes: input a positive or negative edge in interaction with the CA1 line or independently, output a handshake signal in interaction with the CA1 line, output a pulse, output a 0, and output a 1. So that is compatible with the EPP protocol: set it to detect a negative edge, read/write data when it's been pulled low. reset it before the next data/address strobe:

LDA VIA2+$0C

AND #$F0 ; Port A CA1/CA2 control is the bottom four bits

ORA #%00000010 ; CA2=%001 is Independent interrupt input-negative edge, CA1=%0 is Negative Active Edge

STA VIA2+$0C

... and they are set.

But the pin that is given in the diagram as connected through an inverter as an output from the RESB line seems like it is initializing the device connected to the parallel port when the computer is reset, and the /Reset line in an EPP interface should be under device driver control.



For a bespoke interface, you'd want to use CA1 and CA2 working in tandem as Read and Write handshake, the datasheet describes this. You could still use PB0 as the R/W flag. You could use the /Data and /Address strobes in EPP as states rather than as strobes if you are using Port A hardware Read/Write handshaking or could keep them independent by using the PB1 and PB2 that the EPP pinout does not touch.

[BruceMcF]

One thing that is not clear is where PB6 and PB7 are? Are they being used by the system?

If they are not, then the ideal would be to 4, 6, and 8 to be PB4, PB5, and PB6, with 10 as a PB7|Ground on a jumper, so that all 16 of the GPIO are available for uses of the User Port independent of Parallel Port applications.

[BruceMcF]

To clarify this, according to the block header pin numbering above (the standard documents use the DB-25 pin numbering), for the standard EPP port used by a variety of "parallel port"

devices in the 90s:

"Odd" side of block pin header:

1 = Write (PB0)

3-17 (odd) = D0-D7 (PA0-PA7)

19 = Interrupt (from device) on rising edge (CA1)

21 = Wait (handshake from device, cycle starts when Wait=0, is finished when Wait=1), (CA2)

23 = Spare (PB1)

25 = Spare (PB2)



"Even" side of block pin header:

2 = /Data Strobe (value read/write at current port address if /Data=0) (PB3)

4 = Spare (PB4)

6 = /Reset (device reset when low)

8 = /Address Strobe (port address read/write if /Address=0) (PB5)

10-24 = GND

 

The two issues are:

(1) using the CA2 for the Wait handshake is awkward, because the mode of CA2 has to be changed twice a cycle and if the change is too slow, it will miss the edge transition. Meanwhile using a GPIO makes it simple, set it as an input and AND a mask to read whether it is 0 or 1. There is a similar issue using it as a "BUSY" line in a Centronic Paralllel printer interface. The idea appears to be to be that you can drive an interrupt on BUSY, but the BUSY state can easily pass before the interrupt is served and the mode of CA2 is switched from falling edge to rising edge detect, missing the end of the BUSY state. Also, you don't really need to be interrupted to learn about the BUSY state ... a Busy state only matters when trying to output, and in that situation a regular check on a timer interrupt would often make more sense than setting up an IRQ interrupt on BUSY going low. For checking on a regular timer interrupt, it is more convenient if BUSY is on a GPIO.

For the Centronics parallel port interface, it makes more sense to connect pin 23, Paper Out / End to CA2, since that is a state where you are more likely to want to interrupt the regular output process, and to connect pin 21, Busy, to PB1. This fixes the EPP issue at the same time.

(2) Being unable to generate a device /Reset without resetting the CX16 system.

One solution is a jumper between the line resetting the VIA and PB4, which would mirror PB4 on pins 4 and 6. You wouldn't want to do that in Centronics output mode (this would bridge the Fault input and the Initialize output) ... so that would be a jumper to choose between Centronics and EPP mode.

A second solution is a jumper between the line resetting the VIA and CB2, as CB2 can easily be to output either a high or a low. If Power is put on a different line (or pin 26, which is not connected for a normal DB25 cable), then a second block jumper between CB1 and pin 10 would make it possible to put all available resources onto a DB-25 for any CX16 specific interface.