Hardware board version and setup readout
Hardware board version and setup readout
Maybe some register could be reserved as a read-only to find out which board version the software is running on such that bug workarounds can be configured on the fly? If this is a strict hardware function even the kernal can use this to workaround hardware bugs.
So.. read $XXXX => board v1.1 => capacitance bug on D4-D5 to the sound chip. Use delay when accessing etc.
And maybe something like "Got 3x 6581, 0x IEC, 1x Parallel" etc. So if the board is missing IEC, then no software needs to wait for it. And music software can automatically configure for 3x SID.
Hardware board version and setup readout
On 10/19/2022 at 8:06 PM, neutrino said:
Maybe some register could be reserved as a read-only to find out which board version the software is running on such that bug workarounds can be configured on the fly? If this is a strict hardware function even the kernal can use this to workaround hardware bugs.
So.. read $XXXX => board v1.1 => capacitance bug on D4-D5 to the sound chip. Use delay when accessing etc.
And maybe something like "Got 3x 6581, 0x IEC, 1x Parallel" etc. So if the board is missing IEC, then no software needs to wait for it. And music software can automatically configure for 3x SID.
First, this might not be an issue. If the Beta production units do not reveal any major problems, that could be the stable reference design. If they do reveal a major problem, their first choice would likely be to fix the problem before main production begins.
Second, register on what? That doesn't sound like it's commercially practical when you consider that this register would be implemented in 74xx glue logic. A magic location in the ROM with a board version value would be more plausible.
Hardware board version and setup readout
It could be implemented within any existing FPGA on the board. Or perhaps as a serial EEPROM on the same bus the RTC uses etc.
By knowing the hardware revision, kernal and other software can workaround problems. Be it beta or production boards.
Hardware board version and setup readout
There is only one FPGA on the board. It's in the video card and there only a handful of spare bits in the register space remaining. No unused bytes exist within VERAs register space.
I think the cheapest way to do this if it ever becomes necessary is weakly pull up or down some of VIA1's dedicated output pins, put those pins in read mode, and then read out the results of the pull resistors.
Hardware board version and setup readout
On 10/19/2022 at 10:31 PM, neutrino said:
It could be implemented within any existing FPGA on the board. Or perhaps as a serial EEPROM on the same bus the RTC uses etc.
By knowing the hardware revision, kernal and other software can workaround problems. Be it beta or production boards.
But @Wavicle just explained there is ONE FPGA on the board, the substitute for the ASIC tile and sprite video chip that a follow-up to the C128 would have had in the 1980s. And they are not going to increase the build cost for this, so adding a serial EEPROM on the I2C bus is not an option.
One option is adding it to the existing power/keyboard MCU, if there is space on the EEprom or built in Flash storage in the ATTiny -- if its an 861, they have 512 bytes of EEProm data and 8KB of Flash program memory.