My take on a "SID 2.0" (hint: it's the filter)

[m00dawg]

The conversation on Discord today descended a bit into SID terrirtory given the F 256 JR has sockets for real SIDs. To be clear, I love the SID. But for me personally I don't need, nor really even want, a SID in a new retro computer. I know many folks do! The X16 has expansion slots and I'm sure someone will do that. That's not what this post is about. Rather it got me to thinking: the main thing a lot of SID emulations and FPGA solutions miss is the analog filter. Yes you can simulate it, but part of the charm is the quirky nature of that filter. I think there are other analogy bits in the SID but for now, let's focus on the filter problem. I do a lot of Eurorack (modular) stuff and all this gave me a bit of an idea. Forgive me, but without the filter, the SID is mostly a PSG, ala VERA. Some great examples of SID tunes playing on the VERA that sound great, it can do all the fun PWM and drummy sounds. It has 16 channels! It's lovely! As is the YM2151. X16 by itself I think stands on its own as a pretty great chiptune machine.

The PSG is close to the SID but it's not a SID, in part because it has no filter.

So why not make one! I block diagramed out what that might look like in a crappy Google Draw. I won't share it because it's garbage haha but essentially you can take the L and R off the X16 and into an expansion card. One of the inputs goes to the filter, the other goes straight through into a mono summing mixer that then goes into a Spin effect DSP chip (because why not) for global reverb/chorus/delay and stuff. The filter itself could be a discrete ladder filter (ala Moog), an IC solution (like an SSM2144 or SSM2140) - or really anything pretty much. The X16 has -/+ 12V, at least if the power supply used to power it has those as well. This power wouldn't be clean but is of Eurorack standard making most designs drop-in. But many ICs can also work with, say -/+ 9V which can be easily regulated down from the 12V and filtered.

So if you want channels filtered, you send them to whichever output (left or right) is connect to the filter. If you don't, you send it to the other channel. In this way, we have a sort of paraphonic solution (similar to the SID).  The SID used a multimode (low-pass, band-pass, high-pass) filter. I haven't worked out a great way to manage that. The SSM2144 for instance, though iconic, is only low-pass. The SSM2140 can do all 3 but requires a lot more external discrete parts to do that. But the solutions exist for this. Now these won't sound like the SIDs original filter. That isn't the point. I said "SID 2.0" so I want a different filter. I actually think the Doepfer WASP module might be a good fit to couple with the VERA as it gives this awesome gritty sound and the ressonance distorts in this crazy way. It's my favorite filter in my Eurorack, by far. It abuses a hex inverter chip to work and that chip, though inexpensive, tends to fail as a result.

Anyways! Lots of options there. But how would we control the filter and spin chip? An 8-bit multi-channel DAC would do the job. 2 outputs going to the filter and 1-3 do the Spin (depending on which effect parameters make sense to expose). We need some logic outs for the Spin to select from internal effects and/or bonus points for effects off of an EEPROM. Optionally perhaps some slew limiting off the DAC but it's a chiptune solution so I kinda think the aliasing would be part of the charm.

I looked and while the current X16 board revision might expose some I2C bits, I don't see how I2C addressing might work. But if it did, can just get an I2C DAC and Bus Expander and that might be that. But I got to thinking about that and I'd rather use the card memory mapped I/O. This makes it programmatically easy. $9F61 = ressonance, $9F62 = cutoff, $9F63 = Spin parameter 1, etc. You'd control it similar to the VERA which makes integrating it into music tools pretty easy.

However, doing it that way requires having to sit on the actual bus which, from what I recall from previous forum posts here (it's been a while and I can't seem to find them), that isn't trivial. It might be hillariously fun if I used a 6502 as the controller, but not sure how that'd work on the bus (and it would otherwise need it's own program RAM and ROM). I recall it's not as simple as just plonking an 8-bit AVR chip down and connecting the bus lines to it but I could be wrong there.

This doesn't realize a true SID 2.0 since it's a collection of several ICs and components rather than a single chip. But I thought it was an interesting idea and one I haven't seen in retro computing (or really any computer - not using a real analog filter anyway).

Now all this said, if I was going to design a full card complete with its own voices (rather than reuse the VERA), I think I'd take the Eurorack GameBoy wave channel VCO module I'm working on but expand that to support N-number of channels and perhaps 8-bits. Same idea, global filter, etc. but this would be a true expansion card. This is far removed from a SID 2.0 replacement though, and at this point I'd consider it its own thing.

I mostly wrote all this down so I wouldn't forget but still thought I'd share my off the wall idea in case anyone was curious.

[neutrino]

One way to get closer to the real thing is to use a FPGA for the digital part and real circuitry for the analog part like George Pantazopoulos did before he died in a car accident in 2007:

From wikipedia in 2010:

https://en.wikipedia.org/w/index.php?title=MOS_Technology_6581&oldid=336172105

"The PhoenixSID 65X81 project (2006) aimed to faithfully create the SID sound using modern hardware. The workings of a SID chip were recreated on an FPGA, based on interviews with the SID's creator, original datasheets, and comparisons with real SID chips. It was distinguished from similar attempts by its use of real analog circuitry instead of emulation for the legendary SID filter. However, the project was discontinued, because George Pantazopoulos, who was the head of this project, died on April 23, 2007, at the age of 29."

The project details can be found here:

https://web.archive.org/web/20070523192314/https://myhdl.jandecaluwe.com/doku.php/projects:phoenixsid_65x81

https://web.archive.org/web/20141128063052/https://old.myhdl.org/doku.php/projects:phoenixsid_65x81

USB-to-FIFO (FT245BM) --> FPGA (XC3S1000) --> External breadboard for analog circuits.

In the above link there's some samples.

Photo:

[BruceMcF]

Mastering the bus from the expansion port is not simple, but just having normal memory mapped registers on an expansion card shouldn't be too hard.

[m00dawg]

@neutrino

Oh nice, that provides some hope for the future for a proper SID replacement! Tragedy about the car accident.

I whipped together a kinda crappy example of using an external filter with my MB6582. In my case, I used a Doepfer SEM filter since I don't have a filter using the SSM2140 at the moment:

Using an external filter with a SID has been done before of course. MidiBox SID has working solutions for that though most solutions used the SSM2044 I believe. I was more trying to provide an example of how the Vera might sound with a routable filter. Only the main bassline is running through the filter, though I used a global reverb to get an idea of what the Spin chip might do. I was thinking last night I could also provide basic audio routing for the Spin, although it would have limitations based on how the audio is being routed from the sources since I only have the stereo channels from the VERA and YM2151. Looks like these are provided by pin headers on the current prototype board, so hoping they stick around in the final. Basically the Spin would probably have a mixer in front to route either the filter output through the Spin, the dry out, or both. If I provided a filter for the Vera and PSG then there would be more options but still fairly limited compared to a full synth, although that's not really what I'm trying to do.

@BruceMcF

I think I'd only need to read from the bus so that's one less thing. The DAC inputs are easy - just a byte per voltage control. Then for the switches, I think I can use another byte with 3 pins going to the Spin and the remaining 5 being used for the pre-Spin mixer maybe.

Ignoring timing would make things easy ? Just plonk a right-sized AVR on the bus. But that's also not very intelligent. It only needs to do anything with addresses at $9Fxx so I think I could save some pins using some logic before the uC. It's the timing that I'm most worried about.

[BruceMcF]

On 11/17/2022 at 10:25 AM, m00dawg said:

@BruceMcF



I think I'd only need to read from the bus so that's one less thing. The DAC inputs are easy - just a byte per voltage control. Then for the switches, I think I can use another byte with 3 pins going to the Spin and the remaining 5 being used for the pre-Spin mixer maybe.



Ignoring timing would make things easy ? Just plonk a right-sized AVR on the bus. But that's also not very intelligent. It only needs to do anything with addresses at $9Fxx so I think I could save some pins using some logic before the uC. It's the timing that I'm most worried about.

If it fits within a 32byte slot in $9Fxx, then there's a /Select line for being within the slot.

If you need to halt the CPU while waiting for the bus to be read, a flip flop on the RDY flag, pulled low by the /Select line and reset high by a GPIO from the MCU seems like it would do the trick.

[m00dawg]

Yep @Wavicle on Discord actually shared some really good info on how this might work. I got to thinking too...if I can manage to decode the addresses (CPLD?), if I use a parallel DAC I might be able to avoid a microcontroller entirely but that's probably not all that much/any easier.

If I go crazy with the full build I would need several bytes, though less than 32 Roughly looking at something like:



8-bit values:

Vera Cutoff

Vera Ressonance

FM Cutoff

FM Ressonance

Spin Param 1

Spin Param 2

Spin Param 3

Spin Dry/Wet



Bit-values:

Spin Effect Select (3-4 bits depending if EEPROM is used)

Vera Filter to Spin

Vera Unfiltered to Spin

FM Filter to Spin

FM Unfiltered to Spin

So that'd be 9 total, though Wavicle had an interesting simplified approach (available here). Even address is a status/select register (indicating what you want to change) and Odd address is the value. This doubles the access but simplifies the logic (by a lot). Between all the above, the cutoffs are what I would imagine would be updated the most frequently, followed by the ressonance. I've never use a CPLD but seems like one of those could perhaps be used for more complex address filtering perhaps.

Now if I remember the Spin, the frees up 4 bytes. Going down to 1 filter, 2 more. The Spin is a bit ridiculous but it'd provide reverb which gives the X16 an SNES feature (albeit at much higher quality, even if I lower the clockspeed on the Spin). That plus reverb with chiptunes just sounds sooooo good and being able to route signals around, albeit coarsely, could be nice for SFX as well.

[NickMilner]

A bit of sidechain compression would also be handy to let sound effects cut through the mix. ?

[m00dawg]

That's a possible/maybe! I believe the FV-1 Spin chip is the same one used by a popular Eurorack effects module (the FX Aid) and it has a sidechain compressor as one of it's available programs, meaning it's possible to do. The FV-1 doesn't come with one as part of its built-in patches but it's a very configurable chip.

[BruceMcF]

If it's all write only, it seems like you can do the bus interface to an MCU with a couple of parallel in, serial out latches and associated glue logic. One latch captures the contents of the data lines, the other the contents of the four lowest address bits. The IO select for the selected slot (which can be jumpered) is connected directly to a GPIO of the MCU set for edge detect which triggers an interrupt to read the contents of the latches, and there is an /ACK flip flop which /IOSelect pulls high, and an /ACK GPIO can be used to pull low when the contents have been read, with the flip flop going out on all data lines when the slot is read from rather than written to.

Bus interface lines from the MCU:

• 
  SCLK (output, preferably hardware universal serial port)
  


• 
  SDATA (intput, preferably hardware universal serial port)
  


• 
  CLKINHIBIT1 (output, GPIO)
  


• 
  CLKINHIBIT2 (output, GPIO)
  


• 
  /ACK (output, GPIO)
  


• 
  /ALERT (input, preferably rising edge detect interrupt)
  

So it looks something like 6 or so MCU lines dedicated to the bus interface.

[m00dawg]

Yep this is kinda what I was thinking, although your solution is much improved over what I had thought about to this point. Using a uC I'd be going with an SPI DAC more than likely and then just a few pins for the states (though what is on the other end of that I haven't fully figured out yet - referring to running the various channels through the Spin). I think with the Spin in play, a uC is the better solve.

If I remove the Spin (it does add like $15 of cost just for the chip), then it's only 2-4 addresses of 8-bit values. That seems simple enough where a PLD or a logic circuit might be all that's needed, Contents of the data bus can go right into the input of a parallel DAC.

I spent time really digging into the datasheet of the SSM2140. Some homework I need to do on voltage levels as those have to be fairly specific and small (but datasheet also notes saturating the filter can produce distortion which could be fun) and the behavior of the Q VCA with respect to controlling ressonance is a tiny bit vague. I'll need to order a few of these, make a breadboard friendly adapter for it (it's SMD) and start playing around.

I really don't like that it's SMD and there are other options but it'd likely save cost relative to other multimode filter solutions, at least that I've found thus far.