Commander X16

I've been thinking about connecting my X16 to a BeagleBone via the User Port, but I can't find much documentation and no example code.

One thing that confuses me is that the VIA chip has 2x 8 data pins and 4 control lines, but some of those pins share a pin in the user port?

Does anyone have some example code that shows how to set up the User Port pins and how to set up Interrupts and transfer data?

There are two VIA's, VIA#1 and VIA#2.

VIA#1 is the built in one used by the system. It has pins it is not using for the system: PB0, PB1 and PB2, and three of the four handshake lines (CA1, CA2, CB2 ... the system uses CB1). If you look at Chapter 14 of the current Programmer's Reference Guide, this is the 6-pin J4 jumper.

VIA#2 is the optional VIA that connects to the User Port. This is J12:

PB0 -- 1|2 -- PB4
PA0 -- 3|4 -- PB5
PA1 -- 5|6 -- PB6/CB1
PA2 -- 7|8 -- PB7/CB2
PA3 -- 9|10 -- GND
PA4 -- 11|12 -- GND
PA5 -- 13|14 -- GND
PA6 -- 15|16 -- GND
PA7 -- 17|18 -- GND
CA1 -- 19|20 -- GND
PB1 -- 21|22 -- GND
PB2 -- 23|24 -- GND
PB3/CA2 -- 25|26 -- VCC

While not clearly documented in the current version of the PRG, the three pins with alternate lines appear to be for supporting an LPT port in both standard mode and parallel device interface mode as well as allowing for access to the Serial Shift Register.

It seems that the "J3 (Unknown)" is the jumper block for those three lines, but that section of the documentation seems like it could be a prototype version or two behind, since it seems to refer to the User Port as J8 (the front panel jumper) rather than as J12 (that actual User Port jumper), and in any event it doesn't specify which jumpers connect which lines, so a continuity tester would be required to sort out which ones are the PB3/CA2 jumpers, which are the PB6/CB1 jumpers, and which ones are the PB7/CB2 jumpers.

While not clearly documented in the current version of the PRG, the three pins with alternate lines appear to be for supporting an LPT port in both standard mode and parallel device interface mode as well as allowing for access to the Serial Shift Register.

I've found schematics and software for a LPT Cape for the BeagleBone so this seems like the way to do it, but other than the kernal source I still haven't found any code showing how to use/access a VIA chip.

While not X16 specific, I think there are some useful links to example VIA code in the 6502.org discussion on the topic from 2021:

http://forum.6502.org/viewtopic.php?f=2&t=6510

Really, nobody has done anything useful with the User port yet, so you'll have to read the VIA data sheets to work out what you need to do.

Generally speaking, to use the parallel GPIO ports, you need to

1. Set the Data Direction Register. (A 1 in any bit position sets a pin to output. A 0 sets the pin to input.)
2. Read and/or write to the data register

It takes one POKE to set it up, then you can just PEEK and POKE the data register all day long.

Here's a link to the data sheet:

https://eater.net/datasheets/w65c22.pdf

and the X16 documentation:

https://github.com/X16Community/x16-docs/

VIA 0 starts at $9F00, and VIA 1 starts at $9F10. To access a register in the VIA, you add the register number. So if you need to access register 3 of VIA 1, that would be $9F13.

So, to put that together: assume you want to write to PA0-PA7 (pins 3,5,7,9,11,13,15,17):

Write $FF to $9F13. This sets all 8 PAx pins to output.

Then write data to $9F11. That will set the PA pins to the value you just wrote.

When you're done using the User port, it's good practice to clear the DDR by writing 0 to $9F13. This reduces the likelihood of something unfortunate happening by removing voltage from those pins.

Thank you both for the various links and info. I'll give it a read.

Just one quick question if you happen to know. In LPT mode, does the VIA chip handle the control/handshake lines itself or would I have to do that manually?

Regarding LPT on BeagleBone I found this which will make it a lot easier than having to make a Cape:
https://www.av-cables.dk/parallel-adapt ... 80-cm.html

Dacobi wrote: ↑Tue Feb 27, 2024 7:18 am Thank you both for the various links and info. I'll give it a read.

Just one quick question if you happen to know. In LPT mode, does the VIA chip handle the control/handshake lines itself or would I have to do that manually?

Regarding LPT on BeagleBone I found this which will make it a lot easier than having to make a Cape:
https://www.av-cables.dk/parallel-adapt ... 80-cm.html

There currently is no "LPT Mode." There's absolutely no software in the operating system for VIA 2. You'd have to handle everything yourself.

There currently is no "LPT Mode." There's absolutely no software in the operating system for VIA 2. You'd have to handle everything yourself.

I meant hardware wise, if the VIA chip had a LPT mode, where it took care of the control/handshake lines, but I get your drift and I'll start reading through the 65C22 datasheet : )

Turns out that it's not possible to control individual pins on USB to Parallel adapters and the schematic I found for the BeagleBone LPT Cape was for dual full IEEE 1284 ports, which is unnecessarily complicated.

So my current plan is to build my own "Parallel Port" for the BeagleBone using a PCF8575 16 channel I2C IO expander and 4 GPIO pins.

2 GPIO pins will be connected to CA1,CA2 and the 16 pins on the IO expander will be split into Inputs and Outputs with 2 74245 bus drivers to switch between Input or Output, controlled by the remaining 2 GPIO pins.

Finally all pins connecting to the X16s User Port will go through 2 8 channel bidirectional 5V to 3.3V Logic Level Converters.