VERA fast stack implementation
Posted: Wed Mar 13, 2024 10:45 pm
Looks like VERA could be undated to be a fast stack.
When using Data0 and Data1 registers there is a separate pointer for each register.
Could you have a VERA "stack" mode where the registers use the same pointer?
Thus, a data store to Data0 would be a push, and a data load from Data1 would be a pull.
With this setup the program would not need to keep track of a stack pointer - let VERA keep track.
A "load then read" combination would only take one cycle more than the standard "PHA PLA" combination and
would allow a much larger stack.
For users of a 65816 there would be no real advantage, but for 65C02 users the increased stack size might be useful.
When using Data0 and Data1 registers there is a separate pointer for each register.
Could you have a VERA "stack" mode where the registers use the same pointer?
Thus, a data store to Data0 would be a push, and a data load from Data1 would be a pull.
With this setup the program would not need to keep track of a stack pointer - let VERA keep track.
A "load then read" combination would only take one cycle more than the standard "PHA PLA" combination and
would allow a much larger stack.
For users of a 65816 there would be no real advantage, but for 65C02 users the increased stack size might be useful.